5 nm process (English Wikipedia)

Sebastian, Anthony (5 June 2017). "IBM unveils world's first 5nm chip". Ars Technica. Archived from the original on 5 June 2017. Retrieved 5 June 2017.

doi.org

Doris, Bruce B.; Dokumaci, Omer H.; Ieong, Meikei K.; Mocuta, Anda; Zhang, Ying; Kanarsky, Thomas S.; Roy, R. A. (December 2002). Extreme scaling with ultra-thin Si channel MOSFETs. Digest. International Electron Devices Meeting. pp. 267–270. doi:10.1109/IEDM.2002.1175829. ISBN 0-7803-7462-2. S2CID 10151651.
Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). Sub-10-nm planar-bulk-CMOS devices using lateral junction control. IEEE International Electron Devices Meeting 2003. pp. 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446. ISBN 0-7803-7872-5. S2CID 2100267.
Jaehwan Kim; Jin Kim; Byungchul Shin; Sangah Lee; Jae-Hyun Kang; Joong-Won Jeon; Piyush Pathak; Jac Condella; Frank E. Gennari; Philippe Hurat; Ya-Chieh Lai (23 March 2020). Process related yield risk mitigation with in-design pattern replacement for system ICs manufactured at advanced technology nodes. Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280I. San Jose, California, United States. doi:10.1117/12.2551970.
G. Yeap; et al. 5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021µm2 SRAM cells for Mobile SoC and High Performance Computing Applications. 2019 IEEE International Electron Devices Meeting (IEDM). doi:10.1109/IEDM19573.2019.8993577.
J.C. Liu; et al. A Reliability Enhanced 5nm CMOS Technology Featuring 5th Generation FinFET with Fully-Developed EUV and High Mobility Channel for Mobile SoC and High Performance Computing Application. 2020 IEEE International Electron Devices Meeting (IEDM). doi:10.1109/IEDM13553.2020.9372009.

eejournal.com

"No More Nanometers". 23 July 2020.

eetimes.com

"15 Views from a Silicon Summit: Macro to nano perspectives of chip horizon". EE Times. 16 January 2017. Archived from the original on 28 June 2018. Retrieved 4 June 2018.

extremetech.com

Hruska, Joel (25 August 2020). "TSMC Plots an Aggressive Course for 3nm Lithography and Beyond". ExtremeTech. Archived from the original on 22 September 2020. Retrieved 12 September 2020.

hpcwire.com

"Marvell and TSMC Collaborate to Deliver Data Infrastructure Portfolio on 5nm Technology". HPCwire. Archived from the original on 15 September 2020. Retrieved 28 August 2020.

ibm.com

Huiming, Bu (5 June 2017). "5 nanometer transistors inching their way into chips". IBM. Archived from the original on 9 June 2021. Retrieved 9 June 2021.

ieee.org

irds.ieee.org

International Roadmap for Devices and Systems: 2021 Update: More Moore, IEEE, 2021, p. 7, archived from the original on 7 August 2022, retrieved 7 August 2022
"IRDS international roadmap for devices and systems 2017 edition" (PDF). Archived from the original (PDF) on 25 October 2018.
INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2017 EDITION - MORE MOORE (PDF), ITRS, 2017, Section 4.5 Table MM-10 (p.12) entries : "SRAM bitcell area (um2)" ; "SRAM 111 bit cell area density - Mbits/mm2", archived from the original (PDF) on 25 October 2018, retrieved 24 October 2018

spectrum.ieee.org

Samuel K. Moore (21 July 2020). "A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric". IEEE Spectrum. IEEE. Archived from the original on 2 December 2020. Retrieved 20 April 2021.

linkedin.com

"SALELE Double Patterning for 7nm and 5nm Nodes". LinkedIn. Archived from the original on 20 September 2021. Retrieved 25 March 2021.
"Application-Specific Lithography: Patterning 5nm 5.5-Track Metal by DUV".

notebookcheck.net

Solca, Bogdan (22 October 2019). "TSMC already sampling Apple's 5 nm A14 Bionic SoCs for 2020 iPhones". Notebookcheck. Archived from the original on 12 January 2020. Retrieved 12 January 2020.

nvidia.com

nvidianews.nvidia.com

"NVIDIA Delivers Quantum Leap in Performance, Introduces New Era of Neural Rendering With GeForce RTX 40 Series". NVIDIA Newsroom. Retrieved 20 September 2022.

pcgamer.com

Wickens, Katie (30 August 2022). "AMD's Lisa Su confirms chiplet-based RDNA 3 GPU architecture". PC Gamer. Retrieved 20 September 2022.

pcgamesn.com

"TSMC's 7nm, 5nm, and 3nm "are just numbers… it doesn't matter what the number is"". 10 September 2019. Archived from the original on 17 June 2020. Retrieved 20 April 2020.

pcmag.com

uk.pcmag.com

"IBM Figures Out How to Make 5nm Chips". Uk.pcmag.com. 5 June 2017. Archived from the original on 3 December 2017. Retrieved 7 December 2017.

semanticscholar.org

api.semanticscholar.org

Doris, Bruce B.; Dokumaci, Omer H.; Ieong, Meikei K.; Mocuta, Anda; Zhang, Ying; Kanarsky, Thomas S.; Roy, R. A. (December 2002). Extreme scaling with ultra-thin Si channel MOSFETs. Digest. International Electron Devices Meeting. pp. 267–270. doi:10.1109/IEDM.2002.1175829. ISBN 0-7803-7462-2. S2CID 10151651.
Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). Sub-10-nm planar-bulk-CMOS devices using lateral junction control. IEEE International Electron Devices Meeting 2003. pp. 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446. ISBN 0-7803-7872-5. S2CID 2100267.

semi.org

"The Roadmap to 5nm: Convergence of Many Solutions Needed". Semi.org. Archived from the original on 26 November 2015. Retrieved 25 November 2015.

semianalysis.com

Patel, Dylan (27 October 2020). "Apple's A14 Packs 134 Million Transistors/mm², but Falls Short of TSMC's Density Claims". SemiAnalysis. Archived from the original on 12 December 2020. Retrieved 29 October 2020.

semiconductors.org

"International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF). Semiconductors.org. Archived from the original (PDF) on 2 October 2016. Retrieved 7 December 2017.

semiengineering.com

"Quantum Effects At 7/5nm And Beyond". Semiconductor Engineering. Archived from the original on 15 July 2018. Retrieved 15 July 2018.
Mark LaPedus (20 January 2016). "5nm Fab Challenges". Archived from the original on 27 January 2016. Retrieved 22 January 2016. Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS).

semiwiki.com

"IMEC and Cadence Disclose 5nm Test Chip". Semiwiki.com. 4 July 2023. Retrieved 4 July 2023.
Jones, Scotten (13 June 2022). "Intel 4 Deep Dive". SemiWiki.
Jones, Scotten (29 April 2020), "Can TSMC Maintain Their Process Technology Lead", SemiWiki, archived from the original on 13 May 2022, retrieved 11 April 2022
"Samsung Foundry Update 2019". SemiWiki. 6 August 2019. Archived from the original on 29 May 2022. Retrieved 14 May 2022.

techpowerup.com

"Samsung 3 nm GAAFET Node Delayed to 2024". 30 June 2021. Archived from the original on 17 December 2021. Retrieved 8 July 2021.

thefreelibrary.com

"NEC test-produces world's smallest transistor". Thefreelibrary.com. Archived from the original on 15 April 2017. Retrieved 7 December 2017.

theinquirer.net

"IBM claims world's smallest silicon transistor - TheINQUIRER". Theinquirer.net. 9 December 2002. Archived from the original on 31 May 2011. Retrieved 7 December 2017.

theverge.com

Gartenberg, Chaim (29 July 2021). "The summer Intel fell behind". The Verge. Archived from the original on 22 December 2021. Retrieved 22 December 2021.

tsmc.com

pr.tsmc.com

"TSMC and OIP Ecosystem Partners Deliver Industry's First Complete Design Infrastructure for 5nm Process Technology" (Press release). TSMC. 3 April 2019.
"TSMC Expands Advanced Technology Leadership with N4P Process". TSMC (Press release). 26 October 2021.
"TSMC Introduces N4X Process" (Press release). TSMC. 16 December 2021.

tsmc.com

"The Future Is Now (blog post)". TSMC. 16 December 2021. Archived from the original on 7 May 2022. Retrieved 25 May 2022.

web.archive.org

Cutress, Dr Ian. "'Better Yield on 5nm than 7nm': TSMC Update on Defect Rates for N5". AnandTech. Archived from the original on 30 August 2020. Retrieved 28 August 2020.
"Marvell and TSMC Collaborate to Deliver Data Infrastructure Portfolio on 5nm Technology". HPCwire. Archived from the original on 15 September 2020. Retrieved 28 August 2020.
International Roadmap for Devices and Systems: 2021 Update: More Moore, IEEE, 2021, p. 7, archived from the original on 7 August 2022, retrieved 7 August 2022
"TSMC's 7nm, 5nm, and 3nm "are just numbers… it doesn't matter what the number is"". 10 September 2019. Archived from the original on 17 June 2020. Retrieved 20 April 2020.
Samuel K. Moore (21 July 2020). "A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric". IEEE Spectrum. IEEE. Archived from the original on 2 December 2020. Retrieved 20 April 2021.
"Quantum Effects At 7/5nm And Beyond". Semiconductor Engineering. Archived from the original on 15 July 2018. Retrieved 15 July 2018.
"IBM claims world's smallest silicon transistor - TheINQUIRER". Theinquirer.net. 9 December 2002. Archived from the original on 31 May 2011. Retrieved 7 December 2017.
"NEC test-produces world's smallest transistor". Thefreelibrary.com. Archived from the original on 15 April 2017. Retrieved 7 December 2017.
"The Roadmap to 5nm: Convergence of Many Solutions Needed". Semi.org. Archived from the original on 26 November 2015. Retrieved 25 November 2015.
Mark LaPedus (20 January 2016). "5nm Fab Challenges". Archived from the original on 27 January 2016. Retrieved 22 January 2016. Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS).
Sebastian, Anthony (5 June 2017). "IBM unveils world's first 5nm chip". Ars Technica. Archived from the original on 5 June 2017. Retrieved 5 June 2017.
Huiming, Bu (5 June 2017). "5 nanometer transistors inching their way into chips". IBM. Archived from the original on 9 June 2021. Retrieved 9 June 2021.
"IBM Figures Out How to Make 5nm Chips". Uk.pcmag.com. 5 June 2017. Archived from the original on 3 December 2017. Retrieved 7 December 2017.
Shilov, Anton. "Samsung Completes Development of 5nm EUV Process Technology". AnandTech. Archived from the original on 20 April 2019. Retrieved 31 May 2019.
"SALELE Double Patterning for 7nm and 5nm Nodes". LinkedIn. Archived from the original on 20 September 2021. Retrieved 25 March 2021.
Solca, Bogdan (22 October 2019). "TSMC already sampling Apple's 5 nm A14 Bionic SoCs for 2020 iPhones". Notebookcheck. Archived from the original on 12 January 2020. Retrieved 12 January 2020.
Cutress, Dr Ian. "Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020". AnandTech. Archived from the original on 25 May 2020. Retrieved 19 December 2019.
Hruska, Joel (25 August 2020). "TSMC Plots an Aggressive Course for 3nm Lithography and Beyond". ExtremeTech. Archived from the original on 22 September 2020. Retrieved 12 September 2020.
Patel, Dylan (27 October 2020). "Apple's A14 Packs 134 Million Transistors/mm², but Falls Short of TSMC's Density Claims". SemiAnalysis. Archived from the original on 12 December 2020. Retrieved 29 October 2020.
"TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node". WikiChip. 26 October 2021. Archived from the original on 29 May 2022. Retrieved 28 May 2022.
"The Future Is Now (blog post)". TSMC. 16 December 2021. Archived from the original on 7 May 2022. Retrieved 25 May 2022.
Shilov, Anton (17 December 2021). "TSMC Unveils N4X Node". AnandTech. Archived from the original on 25 May 2022. Retrieved 25 May 2022.
Smith, Ryan. "Intel 4 Process Node In Detail: 2x Density Scaling, 20% Improved Performance". AnandTech. Archived from the original on 13 June 2022. Retrieved 13 June 2022.
"IRDS international roadmap for devices and systems 2017 edition" (PDF). Archived from the original (PDF) on 25 October 2018.
Jones, Scotten (29 April 2020), "Can TSMC Maintain Their Process Technology Lead", SemiWiki, archived from the original on 13 May 2022, retrieved 11 April 2022
"Samsung Foundry Update 2019". SemiWiki. 6 August 2019. Archived from the original on 29 May 2022. Retrieved 14 May 2022.
"5 nm lithography process". WikiChip. Archived from the original on 6 November 2020. Retrieved 30 April 2017.
INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2017 EDITION - MORE MOORE (PDF), ITRS, 2017, Section 4.5 Table MM-10 (p.12) entries : "SRAM bitcell area (um2)" ; "SRAM 111 bit cell area density - Mbits/mm2", archived from the original (PDF) on 25 October 2018, retrieved 24 October 2018
Cutress, Dr Ian. "Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!". AnandTech. Archived from the original on 3 November 2021. Retrieved 27 July 2021.
Gartenberg, Chaim (29 July 2021). "The summer Intel fell behind". The Verge. Archived from the original on 22 December 2021. Retrieved 22 December 2021.
"International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF). Semiconductors.org. Archived from the original (PDF) on 2 October 2016. Retrieved 7 December 2017.
"5 nm lithography process". WikiChip. Archived from the original on 6 November 2020. Retrieved 7 December 2017.
"Samsung 3 nm GAAFET Node Delayed to 2024". 30 June 2021. Archived from the original on 17 December 2021. Retrieved 8 July 2021.
Shilov, Anton. "Samsung: Deployment of 3nm GAE Node on Track for 2022". AnandTech. Archived from the original on 27 July 2021. Retrieved 27 July 2021.
Shilov, Anton. "TSMC Update: 2nm in Development, 3nm and 4nm on Track for 2022". AnandTech. Archived from the original on 27 July 2021. Retrieved 27 July 2021.
"15 Views from a Silicon Summit: Macro to nano perspectives of chip horizon". EE Times. 16 January 2017. Archived from the original on 28 June 2018. Retrieved 4 June 2018.

wikichip.org

fuse.wikichip.org

"TSMC Details 5 nm". 21 March 2020.
"TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node". WikiChip. 26 October 2021. Archived from the original on 29 May 2022. Retrieved 28 May 2022.
Schor, David (19 June 2022). "A Look At Intel 4 Process Technology". WikiChip Fuse.
"Samsung 5 nm and 4 nm Update". WikiChip. 19 October 2019.
"Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements". 5 July 2022.
"N3E Replaces N3; Comes in Many Flavors". 4 September 2022.
"Did We Just Witness The Death Of SRAM?". 4 December 2022.
"TSMC N3, and Challenges Ahead". 27 May 2023.

en.wikichip.org

"5 nm lithography process". WikiChip. Archived from the original on 6 November 2020. Retrieved 30 April 2017.
"5 nm lithography process". WikiChip. Archived from the original on 6 November 2020. Retrieved 7 December 2017.