"The Illiac is a binary parallel asynchronous computer in which negative numbers are represented as two's complements." – final summary of "Illiac Design Techniques" 1955.
"In the 1950 and 1960s, asynchronous design was used in many early mainframe computers, including the ILLIAC I and ILLIAC II ... ." Brief History of asynchronous circuit design
Vasyukevich, Vadim O. (2011). Written at Riga, Latvia. Asynchronous Operators of Sequential Logic: Venjunction & Sequention — Digital Circuits Analysis and Design. Lecture Notes in Electrical Engineering. Vol. 101 (1st ed.). Berlin / Heidelberg, Germany: Springer-Verlag. doi:10.1007/978-3-642-21611-4. ISBN978-3-642-21610-7. ISSN1876-1100. LCCN2011929655. (xiii+1+123+7 pages) (NB. The back cover of this book erroneously states volume 4, whereas it actually is volume 101.)
"Keep It Strictly Synchronous: KISS those asynchronous-logic problems good-bye".
Personal Engineering and Instrumentation News, November 1997, pages 53–55.
http://www.fpga-site.com/kiss.html
SEAforth OverviewArchived 2008-02-02 at the Wayback Machine "... asynchronous circuit design throughout the chip. There is no central clock with billions of dumb nodes dissipating useless power. ... the processor cores are internally asynchronous themselves."
keil.com
"Handshake Solutions HT80C51" "The Handshake Solutions HT80C51 is a Low power, asynchronous 80C51 implementation using handshake technology, compatible with the standard 8051 instruction set."
loc.gov
lccn.loc.gov
Vasyukevich, Vadim O. (2011). Written at Riga, Latvia. Asynchronous Operators of Sequential Logic: Venjunction & Sequention — Digital Circuits Analysis and Design. Lecture Notes in Electrical Engineering. Vol. 101 (1st ed.). Berlin / Heidelberg, Germany: Springer-Verlag. doi:10.1007/978-3-642-21611-4. ISBN978-3-642-21610-7. ISSN1876-1100. LCCN2011929655. (xiii+1+123+7 pages) (NB. The back cover of this book erroneously states volume 4, whereas it actually is volume 101.)
"Entirely asynchronous, its hundred-odd boards would send out requests, earmark the results for somebody else, swipe somebody else's signals or data, and backstab each other in all sorts of amusing ways which occasionally failed (the "op not complete" timer would go off and cause a fault). ... [There] was no hint of an organized synchronization strategy: various "it's ready now", "ok, go", "take a cycle" pulses merely surged through the vast backpanel ANDed with appropriate state and goosed the next guy down. Not without its charms, this seemingly ad-hoc technology facilitated a substantial degree of overlap ... as well as the [segmentation and paging] of the Multics address mechanism to the extant 6000 architecture in an ingenious, modular, and surprising way ... . Modification and debugging of the processor, though, were no fun." "Multics Glossary: ... 6180"
SEAforth OverviewArchived 2008-02-02 at the Wayback Machine "... asynchronous circuit design throughout the chip. There is no central clock with billions of dumb nodes dissipating useless power. ... the processor cores are internally asynchronous themselves."
Vasyukevich, Vadim O. (2011). Written at Riga, Latvia. Asynchronous Operators of Sequential Logic: Venjunction & Sequention — Digital Circuits Analysis and Design. Lecture Notes in Electrical Engineering. Vol. 101 (1st ed.). Berlin / Heidelberg, Germany: Springer-Verlag. doi:10.1007/978-3-642-21611-4. ISBN978-3-642-21610-7. ISSN1876-1100. LCCN2011929655. (xiii+1+123+7 pages) (NB. The back cover of this book erroneously states volume 4, whereas it actually is volume 101.)