Asynchronous circuit (English Wikipedia)

"The Illiac is a binary parallel asynchronous computer in which negative numbers are represented as two's complements." – final summary of "Illiac Design Techniques" 1955.

books.google.com

Fant, Karl M. (February 2005). Logically determined design: clockless system design with NULL convention logic (NCL) (1 ed.). Hoboken, New Jersey, USA: Wiley-Interscience / John Wiley and Sons, Inc. ISBN 978-0-471-68478-7. LCCN 2004050923. (xvi+292 pages)
Smith, Scott C.; Di, Jia (2009). Designing Asynchronous Circuits using NULL Conventional Logic (NCL) (PDF). Synthesis Lectures on Digital Circuits & Systems. Morgan & Claypool Publishers [d]. pp. 61–73. eISSN 1932-3174. ISBN 978-1-59829-981-6. ISSN 1932-3166. Lecture #23. Retrieved 2023-09-10; Smith, Scott C.; Di, Jia (2022) [2009-07-23]. Designing Asynchronous Circuits using NULL Conventional Logic (NCL). Synthesis Lectures on Digital Circuits & Systems. University of Arkansas, Arkansas, USA: Springer Nature Switzerland AG. doi:10.1007/978-3-031-79800-9. eISSN 1932-3174. ISBN 978-3-031-79799-6. ISSN 1932-3166. Lecture #23. Retrieved 2023-09-10. (x+86+6 pages)
"In the 1950 and 1960s, asynchronous design was used in many early mainframe computers, including the ILLIAC I and ILLIAC II ... ." Brief History of asynchronous circuit design

caltech.edu

resolver.caltech.edu

Martin, Alain J. (2014-02-06). "25 Years Ago: The First Asynchronous Microprocessor". Computer Science Technical Reports. California Institute of Technology. doi:10.7907/Z9QR4V3H. {{cite journal}}: Cite journal requires |journal= (help)

columbia.edu

cs.columbia.edu

Nowick, S. M.; Singh, M. (May–June 2015). "Asynchronous Design — Part 1: Overview and Recent Advances" (PDF). IEEE Design and Test. 32 (3): 5–18. doi:10.1109/MDAT.2015.2413759. S2CID 14644656. Archived from the original (PDF) on 2018-12-21. Retrieved 2019-08-27.
Nowick, S. M.; Singh, M. (May–June 2015). "Asynchronous Design — Part 2: Systems and Methodologies" (PDF). IEEE Design and Test. 32 (3): 19–28. doi:10.1109/MDAT.2015.2413757. S2CID 16732793. Archived from the original (PDF) on 2018-12-21. Retrieved 2019-08-27.
van Berkel, C. H.; Josephs, M. B.; Nowick, S. M. (February 1999). "Applications of Asynchronous Circuits" (PDF). Proceedings of the IEEE. 87 (2): 234–242. doi:10.1109/5.740016. Archived from the original (PDF) on 2018-04-03. Retrieved 2019-08-27.
Nowick, S. M.; Singh, M. (September–October 2011). "High-Performance Asynchronous Pipelines: an Overview" (PDF). IEEE Design & Test of Computers. 28 (5): 8–22. doi:10.1109/mdt.2011.71. S2CID 6515750. Archived from the original (PDF) on 2021-04-21. Retrieved 2019-08-27.
Nowick, S. M.; Yun, K. Y.; Beerel, P. A.; Dooply, A. E. (March 1997). "Speculative completion for the design of high-performance asynchronous dynamic adders" (PDF). Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems. pp. 210–223. doi:10.1109/ASYNC.1997.587176. ISBN 0-8186-7922-0. S2CID 1098994. Archived from the original (PDF) on 2021-04-21. Retrieved 2019-08-27.
Nowick, S. M. (September 1996). "Design of a Low-Latency Asynchronous Adder Using Speculative Completion" (PDF). IEE Proceedings - Computers and Digital Techniques. 143 (5): 301–307. doi:10.1049/ip-cdt:19960704. Archived from the original (PDF) on 2021-04-22. Retrieved 2019-08-27.
Sheikh, B.; Manohar, R. (May 2010). "An Operand-Optimized Asynchronous IEEE 754 Double-Precision Floating-Point Adder" (PDF). Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems ('Async'): 151–162. Archived from the original (PDF) on 2021-04-21. Retrieved 2019-08-27.

computer-museum.ru

Chapter 4.5.3 in the biography of D. I. Juditsky (in Russian)

cpu80.ru

"Серия 587 - Collection ex-USSR Chip's". Archived from the original on 2015-07-17. Retrieved 2015-07-16.
"Серия 588 - Collection ex-USSR Chip's". Archived from the original on 2015-07-17. Retrieved 2015-07-16.
"Серия 1883/U830 - Collection ex-USSR Chip's". Archived from the original on 2015-07-22. Retrieved 2015-07-19.

darpa.mil

"SyNAPSE program develops advanced brain-inspired chip" Archived 2014-08-10 at the Wayback Machine. August 07, 2014.

doi.org

Nowick, S. M.; Singh, M. (May–June 2015). "Asynchronous Design — Part 1: Overview and Recent Advances" (PDF). IEEE Design and Test. 32 (3): 5–18. doi:10.1109/MDAT.2015.2413759. S2CID 14644656. Archived from the original (PDF) on 2018-12-21. Retrieved 2019-08-27.
Nowick, S. M.; Singh, M. (May–June 2015). "Asynchronous Design — Part 2: Systems and Methodologies" (PDF). IEEE Design and Test. 32 (3): 19–28. doi:10.1109/MDAT.2015.2413757. S2CID 16732793. Archived from the original (PDF) on 2018-12-21. Retrieved 2019-08-27.
van Berkel, C. H.; Josephs, M. B.; Nowick, S. M. (February 1999). "Applications of Asynchronous Circuits" (PDF). Proceedings of the IEEE. 87 (2): 234–242. doi:10.1109/5.740016. Archived from the original (PDF) on 2018-04-03. Retrieved 2019-08-27.
Vasyukevich, Vadim O. (April 2007). "Decoding asynchronous sequences". Automatic Control and Computer Sciences. 41 (2). Allerton Press: 93–99. doi:10.3103/S0146411607020058. ISSN 1558-108X. S2CID 21204394.
Vasyukevich, Vadim O. (2011). Written at Riga, Latvia. Asynchronous Operators of Sequential Logic: Venjunction & Sequention — Digital Circuits Analysis and Design. Lecture Notes in Electrical Engineering. Vol. 101 (1st ed.). Berlin / Heidelberg, Germany: Springer-Verlag. doi:10.1007/978-3-642-21611-4. ISBN 978-3-642-21610-7. ISSN 1876-1100. LCCN 2011929655. (xiii+1+123+7 pages) (NB. The back cover of this book erroneously states volume 4, whereas it actually is volume 101.)
Smith, Scott C.; Di, Jia (2009). Designing Asynchronous Circuits using NULL Conventional Logic (NCL) (PDF). Synthesis Lectures on Digital Circuits & Systems. Morgan & Claypool Publishers [d]. pp. 61–73. eISSN 1932-3174. ISBN 978-1-59829-981-6. ISSN 1932-3166. Lecture #23. Retrieved 2023-09-10; Smith, Scott C.; Di, Jia (2022) [2009-07-23]. Designing Asynchronous Circuits using NULL Conventional Logic (NCL). Synthesis Lectures on Digital Circuits & Systems. University of Arkansas, Arkansas, USA: Springer Nature Switzerland AG. doi:10.1007/978-3-031-79800-9. eISSN 1932-3174. ISBN 978-3-031-79799-6. ISSN 1932-3166. Lecture #23. Retrieved 2023-09-10. (x+86+6 pages)
Chu, T.-A. (1986-06-01). "On the models for designing VLSI asynchronous digital systems". Integration. 4 (2): 99–113. doi:10.1016/S0167-9260(86)80002-5. ISSN 0167-9260.
Yakovlev, Alexandre; Lavagno, Luciano; Sangiovanni-Vincentelli, Alberto (1996-11-01). "A unified signal transition graph model for asynchronous control circuit synthesis". Formal Methods in System Design. 9 (3): 139–188. doi:10.1007/BF00122081. ISSN 1572-8102. S2CID 26970846.
Cortadella, J.; Kishinevsky, M.; Kondratyev, A.; Lavagno, L.; Yakovlev, A. (2002). Logic Synthesis for Asynchronous Controllers and Interfaces. Springer Series in Advanced Microelectronics. Vol. 8. Berlin / Heidelberg, Germany: Springer Berlin Heidelberg. doi:10.1007/978-3-642-55989-1. ISBN 978-3-642-62776-7.
Nowick, S. M.; Singh, M. (September–October 2011). "High-Performance Asynchronous Pipelines: an Overview" (PDF). IEEE Design & Test of Computers. 28 (5): 8–22. doi:10.1109/mdt.2011.71. S2CID 6515750. Archived from the original (PDF) on 2021-04-21. Retrieved 2019-08-27.
Nowick, S. M.; Yun, K. Y.; Beerel, P. A.; Dooply, A. E. (March 1997). "Speculative completion for the design of high-performance asynchronous dynamic adders" (PDF). Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems. pp. 210–223. doi:10.1109/ASYNC.1997.587176. ISBN 0-8186-7922-0. S2CID 1098994. Archived from the original (PDF) on 2021-04-21. Retrieved 2019-08-27.
Nowick, S. M. (September 1996). "Design of a Low-Latency Asynchronous Adder Using Speculative Completion" (PDF). IEE Proceedings - Computers and Digital Techniques. 143 (5): 301–307. doi:10.1049/ip-cdt:19960704. Archived from the original (PDF) on 2021-04-22. Retrieved 2019-08-27.
Martin, A. J.; Nystrom, M.; Wong, C. G. (November 2003). "Three generations of asynchronous microprocessors". IEEE Design & Test of Computers. 20 (6): 9–17. doi:10.1109/MDT.2003.1246159. ISSN 0740-7475. S2CID 15164301.
Martin, A. J.; Nystrom, M.; Papadantonakis, K.; Penzes, P. I.; Prakash, P.; Wong, C. G.; Chang, J.; Ko, K. S.; Lee, B.; Ou, E.; Pugh, J. (2003). "The Lutonium: A sub-nanojoule asynchronous 8051 microcontroller". Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings (PDF). Vancouver, BC, Canada: IEEE Comput. Soc. pp. 14–23. doi:10.1109/ASYNC.2003.1199162. ISBN 978-0-7695-1898-5. S2CID 13866418.
Martin, Alain J. (2014-02-06). "25 Years Ago: The First Asynchronous Microprocessor". Computer Science Technical Reports. California Institute of Technology. doi:10.7907/Z9QR4V3H. {{cite journal}}: Cite journal requires |journal= (help)
Zhang, Qianyi; Theodoropoulos, Georgios (2003). "Towards an Asynchronous MIPS Processor". In Omondi, Amos; Sedukhin, Stanislav (eds.). Advances in Computer Systems Architecture. Lecture Notes in Computer Science. Berlin, Heidelberg: Springer. pp. 137–150. doi:10.1007/978-3-540-39864-6_12. ISBN 978-3-540-39864-6.
Lines, Andrew (March 2007). "The Vortex: A Superscalar Asynchronous Processor". 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07). pp. 39–48. doi:10.1109/ASYNC.2007.28. ISBN 978-0-7695-2771-0. S2CID 33189213.
Lines, A. (2003). "Nexus: An asynchronous crossbar interconnect for synchronous system-on-chip designs". 11th Symposium on High Performance Interconnects, 2003. Proceedings. Stanford, CA, USA: IEEE Comput. Soc. pp. 2–9. doi:10.1109/CONECT.2003.1231470. ISBN 978-0-7695-2012-4. S2CID 1799204.

dtu.dk

orbit.dtu.dk

Sparsø, Jens (April 2006). "Asynchronous Circuit Design A Tutorial" (PDF). Technical University of Denmark.

ed.ac.uk

era.lib.ed.ac.uk

"A Network-based Asynchronous Architecture for Cryptographic Devices" by Ljiljana Spadavecchia 2005 in section "4.10.2 Side-channel analysis of dual-rail asynchronous architectures" and section "5.5.5.1 Instruction set"

eetimes.com

Kruger, Robert (2005-03-15). "Reality TV for FPGA design engineers!". eetimes.com. Retrieved 2020-11-11.
"Seiko Epson tips flexible processor via TFT technology" Archived 2010-02-01 at the Wayback Machine by Mark LaPedus 2005

epfl.ch

infoscience.epfl.ch

Martin, A. J.; Nystrom, M.; Papadantonakis, K.; Penzes, P. I.; Prakash, P.; Wong, C. G.; Chang, J.; Ko, K. S.; Lee, B.; Ou, E.; Pugh, J. (2003). "The Lutonium: A sub-nanojoule asynchronous 8051 microcontroller". Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings (PDF). Vancouver, BC, Canada: IEEE Comput. Soc. pp. 14–23. doi:10.1109/ASYNC.2003.1199162. ISBN 978-0-7695-1898-5. S2CID 13866418.

epson.co.jp

"Epson Develops the World's First Flexible 8-Bit Asynchronous Microprocessor"

epson.com

global.epson.com

"Epson Develops the World's First Flexible 8-Bit Asynchronous Microprocessor"^{[permanent dead link]} 2005

espacenet.com

worldwide.espacenet.com

A. A. Vasenkov, V. L. Dshkhunian, P. R. Mashevich, P. V. Nesterov, V. V. Telenkov, Ju. E. Chicherin, D. I. Juditsky, "Microprocessor computing system," Patent US4124890, Nov. 7, 1978

forth.gr

ics.forth.gr

"Asynchronous Open-Source DLX Processor (ASPIDA)".

fpga-site.com

"Keep It Strictly Synchronous: KISS those asynchronous-logic problems good-bye". Personal Engineering and Instrumentation News, November 1997, pages 53–55. http://www.fpga-site.com/kiss.html

galois.com

"Why Asynchronous Design?". Galois, Inc. 2021-07-15. Retrieved 2021-12-04.

gbv.de

Smith, Scott C.; Di, Jia (2009). Designing Asynchronous Circuits using NULL Conventional Logic (NCL) (PDF). Synthesis Lectures on Digital Circuits & Systems. Morgan & Claypool Publishers [d]. pp. 61–73. eISSN 1932-3174. ISBN 978-1-59829-981-6. ISSN 1932-3166. Lecture #23. Retrieved 2023-09-10; Smith, Scott C.; Di, Jia (2022) [2009-07-23]. Designing Asynchronous Circuits using NULL Conventional Logic (NCL). Synthesis Lectures on Digital Circuits & Systems. University of Arkansas, Arkansas, USA: Springer Nature Switzerland AG. doi:10.1007/978-3-031-79800-9. eISSN 1932-3174. ISBN 978-3-031-79799-6. ISSN 1932-3166. Lecture #23. Retrieved 2023-09-10. (x+86+6 pages)

greenarraychips.com

"GreenArrayChips" "Ultra-low-powered multi-computer chips with integrated peripherals."

holtronic.ch

"Introduction of TFT R&D Activities in Seiko Epson Corporation" by Tatsuya Shimoda (2005?) has picture of "A flexible 8-bit asynchronous microprocessor, ACT11"

ieee.org

ieeexplore.ieee.org

Martin, A. J.; Nystrom, M.; Wong, C. G. (November 2003). "Three generations of asynchronous microprocessors". IEEE Design & Test of Computers. 20 (6): 9–17. doi:10.1109/MDT.2003.1246159. ISSN 0740-7475. S2CID 15164301.
Martin, A. J.; Nystrom, M.; Papadantonakis, K.; Penzes, P. I.; Prakash, P.; Wong, C. G.; Chang, J.; Ko, K. S.; Lee, B.; Ou, E.; Pugh, J. (2003). "The Lutonium: A sub-nanojoule asynchronous 8051 microcontroller". Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings (PDF). Vancouver, BC, Canada: IEEE Comput. Soc. pp. 14–23. doi:10.1109/ASYNC.2003.1199162. ISBN 978-0-7695-1898-5. S2CID 13866418.
"A flexible 8b asynchronous microprocessor based on low-temperature poly-silicon TFT technology" by Karaki et al. 2005. Abstract: "A flexible 8b asynchronous microprocessor ACTII ... The power level is 30% of the synchronous counterpart."
Lines, Andrew (March 2007). "The Vortex: A Superscalar Asynchronous Processor". 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07). pp. 39–48. doi:10.1109/ASYNC.2007.28. ISBN 978-0-7695-2771-0. S2CID 33189213.
Lines, A. (2003). "Nexus: An asynchronous crossbar interconnect for synchronous system-on-chip designs". 11th Symposium on High Performance Interconnects, 2003. Proceedings. Stanford, CA, USA: IEEE Comput. Soc. pp. 2–9. doi:10.1109/CONECT.2003.1231470. ISBN 978-0-7695-2012-4. S2CID 1799204.

intellasys.net

SEAforth Overview Archived 2008-02-02 at the Wayback Machine "... asynchronous circuit design throughout the chip. There is no central clock with billions of dumb nodes dissipating useless power. ... the processor cores are internally asynchronous themselves."

keil.com

"Handshake Solutions HT80C51" "The Handshake Solutions HT80C51 is a Low power, asynchronous 80C51 implementation using handshake technology, compatible with the standard 8051 instruction set."

loc.gov

lccn.loc.gov

Vasyukevich, Vadim O. (2011). Written at Riga, Latvia. Asynchronous Operators of Sequential Logic: Venjunction & Sequention — Digital Circuits Analysis and Design. Lecture Notes in Electrical Engineering. Vol. 101 (1st ed.). Berlin / Heidelberg, Germany: Springer-Verlag. doi:10.1007/978-3-642-21611-4. ISBN 978-3-642-21610-7. ISSN 1876-1100. LCCN 2011929655. (xiii+1+123+7 pages) (NB. The back cover of this book erroneously states volume 4, whereas it actually is volume 101.)
Fant, Karl M. (February 2005). Logically determined design: clockless system design with NULL convention logic (NCL) (1 ed.). Hoboken, New Jersey, USA: Wiley-Interscience / John Wiley and Sons, Inc. ISBN 978-0-471-68478-7. LCCN 2004050923. (xvi+292 pages)
Fant, Karl M. (August 2007). Computer Science Reconsidered: The Invocation Model of Process Expression (1 ed.). Hoboken, New Jersey, USA: Wiley-Interscience / John Wiley and Sons, Inc. ISBN 978-0-471-79814-9. LCCN 2006052821. Retrieved 2023-07-23. (xix+1+269 pages)

man.ac.uk

cs.man.ac.uk

LARD Archived March 6, 2005, at the Wayback Machine
"Computer Resurrection Issue 18".

multicians.org

"Entirely asynchronous, its hundred-odd boards would send out requests, earmark the results for somebody else, swipe somebody else's signals or data, and backstab each other in all sorts of amusing ways which occasionally failed (the "op not complete" timer would go off and cause a fault). ... [There] was no hint of an organized synchronization strategy: various "it's ready now", "ok, go", "take a cycle" pulses merely surged through the vast backpanel ANDed with appropriate state and goosed the next guy down. Not without its charms, this seemingly ad-hoc technology facilitated a substantial degree of overlap ... as well as the [segmentation and paging] of the Multics address mechanism to the extant 6000 architecture in an ingenious, modular, and surprising way ... . Modification and debugging of the processor, though, were no fun." "Multics Glossary: ... 6180"
"10/81 ... DPS 8/70M CPUs" Multics Chronology
"The Series 60, Level 68 was just a repackaging of the 6180." Multics Hardware features: Series 60, Level 68

ncl.ac.uk

staff.ncl.ac.uk

Rosenblum, L. Ya.; Yakovlev, A. V. (July 1985). "Signal Graphs: from Self-timed to Timed ones. Proceedings of International Workshop on Timed Petri Nets" (PDF). Torino, Italy: IEEE CS Press. pp. 199–207. Archived (PDF) from the original on 2003-10-23.

nctu.edu.tw

owlhouse.csie.nctu.edu.tw

Furber, Steve. "Principles of Asynchronous Circuit Design" (PDF). Pg. 232. Archived from the original (PDF) on 2012-04-26. Retrieved 2011-12-13.

opencores.org

"ASPIDA sync/async DLX Core". OpenCores.org. Retrieved 2014-09-05.

pcadvisor.co.uk

"Seiko Epson details flexible microprocessor: A4 sheets of e-paper in the pipeline by Paul Kallender 2005

rand.org

Johnniac history written in 1968

sciencedirect.com

Chu, T.-A. (1986-06-01). "On the models for designing VLSI asynchronous digital systems". Integration. 4 (2): 99–113. doi:10.1016/S0167-9260(86)80002-5. ISSN 0167-9260.

semanticscholar.org

api.semanticscholar.org

Nowick, S. M.; Singh, M. (May–June 2015). "Asynchronous Design — Part 1: Overview and Recent Advances" (PDF). IEEE Design and Test. 32 (3): 5–18. doi:10.1109/MDAT.2015.2413759. S2CID 14644656. Archived from the original (PDF) on 2018-12-21. Retrieved 2019-08-27.
Nowick, S. M.; Singh, M. (May–June 2015). "Asynchronous Design — Part 2: Systems and Methodologies" (PDF). IEEE Design and Test. 32 (3): 19–28. doi:10.1109/MDAT.2015.2413757. S2CID 16732793. Archived from the original (PDF) on 2018-12-21. Retrieved 2019-08-27.
Vasyukevich, Vadim O. (April 2007). "Decoding asynchronous sequences". Automatic Control and Computer Sciences. 41 (2). Allerton Press: 93–99. doi:10.3103/S0146411607020058. ISSN 1558-108X. S2CID 21204394.
Yakovlev, Alexandre; Lavagno, Luciano; Sangiovanni-Vincentelli, Alberto (1996-11-01). "A unified signal transition graph model for asynchronous control circuit synthesis". Formal Methods in System Design. 9 (3): 139–188. doi:10.1007/BF00122081. ISSN 1572-8102. S2CID 26970846.
Nowick, S. M.; Singh, M. (September–October 2011). "High-Performance Asynchronous Pipelines: an Overview" (PDF). IEEE Design & Test of Computers. 28 (5): 8–22. doi:10.1109/mdt.2011.71. S2CID 6515750. Archived from the original (PDF) on 2021-04-21. Retrieved 2019-08-27.
Nowick, S. M.; Yun, K. Y.; Beerel, P. A.; Dooply, A. E. (March 1997). "Speculative completion for the design of high-performance asynchronous dynamic adders" (PDF). Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems. pp. 210–223. doi:10.1109/ASYNC.1997.587176. ISBN 0-8186-7922-0. S2CID 1098994. Archived from the original (PDF) on 2021-04-21. Retrieved 2019-08-27.
Martin, A. J.; Nystrom, M.; Wong, C. G. (November 2003). "Three generations of asynchronous microprocessors". IEEE Design & Test of Computers. 20 (6): 9–17. doi:10.1109/MDT.2003.1246159. ISSN 0740-7475. S2CID 15164301.
Martin, A. J.; Nystrom, M.; Papadantonakis, K.; Penzes, P. I.; Prakash, P.; Wong, C. G.; Chang, J.; Ko, K. S.; Lee, B.; Ou, E.; Pugh, J. (2003). "The Lutonium: A sub-nanojoule asynchronous 8051 microcontroller". Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings (PDF). Vancouver, BC, Canada: IEEE Comput. Soc. pp. 14–23. doi:10.1109/ASYNC.2003.1199162. ISBN 978-0-7695-1898-5. S2CID 13866418.
Lines, Andrew (March 2007). "The Vortex: A Superscalar Asynchronous Processor". 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07). pp. 39–48. doi:10.1109/ASYNC.2007.28. ISBN 978-0-7695-2771-0. S2CID 33189213.
Lines, A. (2003). "Nexus: An asynchronous crossbar interconnect for synchronous system-on-chip designs". 11th Symposium on High Performance Interconnects, 2003. Proceedings. Stanford, CA, USA: IEEE Comput. Soc. pp. 2–9. doi:10.1109/CONECT.2003.1231470. ISBN 978-0-7695-2012-4. S2CID 1799204.

springer.com

link.springer.com

Cortadella, J.; Kishinevsky, M.; Kondratyev, A.; Lavagno, L.; Yakovlev, A. (2002). Logic Synthesis for Asynchronous Controllers and Interfaces. Springer Series in Advanced Microelectronics. Vol. 8. Berlin / Heidelberg, Germany: Springer Berlin Heidelberg. doi:10.1007/978-3-642-55989-1. ISBN 978-3-642-62776-7.
Zhang, Qianyi; Theodoropoulos, Georgios (2003). "Towards an Asynchronous MIPS Processor". In Omondi, Amos; Sedukhin, Stanislav (eds.). Advances in Computer Systems Architecture. Lecture Notes in Computer Science. Berlin, Heidelberg: Springer. pp. 137–150. doi:10.1007/978-3-540-39864-6_12. ISBN 978-3-540-39864-6.

stanford.edu

web.stanford.edu

Horowitz, Mark (2007). "Advanced VLSI Circuit Design Lecture". Stanford University, Computer Systems Laboratory. Archived from the original on 2016-04-21.

tiempo-ic.com

Tiempo: Asynchronous TAM16 Core IP

tudelft.nl

repository.tudelft.nl

van Leeuwen, T. M. (2010). Implementation and automatic generation of asynchronous scheduled dataflow graph. Delft.

upc.edu

cs.upc.edu

"Petrify: Related publications". www.cs.upc.edu. Retrieved 2021-07-28.

uspto.gov

patft.uspto.gov

Smith, Scott C.; Di, Jia. "U.S. 7,977,972 Ultra-Low Power Multi-threshold Asychronous Circuit Design". Retrieved 2011-12-12.

web.archive.org

Horowitz, Mark (2007). "Advanced VLSI Circuit Design Lecture". Stanford University, Computer Systems Laboratory. Archived from the original on 2016-04-21.
van Berkel, C. H.; Josephs, M. B.; Nowick, S. M. (February 1999). "Applications of Asynchronous Circuits" (PDF). Proceedings of the IEEE. 87 (2): 234–242. doi:10.1109/5.740016. Archived from the original (PDF) on 2018-04-03. Retrieved 2019-08-27.
Vasyukevich, Vadim O. (2009). "Asynchronous logic elements. Venjunction and sequention" (PDF). Archived (PDF) from the original on 2011-07-22. (118 pages)
Rosenblum, L. Ya.; Yakovlev, A. V. (July 1985). "Signal Graphs: from Self-timed to Timed ones. Proceedings of International Workshop on Timed Petri Nets" (PDF). Torino, Italy: IEEE CS Press. pp. 199–207. Archived (PDF) from the original on 2003-10-23.
Nowick, S. M.; Singh, M. (September–October 2011). "High-Performance Asynchronous Pipelines: an Overview" (PDF). IEEE Design & Test of Computers. 28 (5): 8–22. doi:10.1109/mdt.2011.71. S2CID 6515750. Archived from the original (PDF) on 2021-04-21. Retrieved 2019-08-27.
Nowick, S. M.; Yun, K. Y.; Beerel, P. A.; Dooply, A. E. (March 1997). "Speculative completion for the design of high-performance asynchronous dynamic adders" (PDF). Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems. pp. 210–223. doi:10.1109/ASYNC.1997.587176. ISBN 0-8186-7922-0. S2CID 1098994. Archived from the original (PDF) on 2021-04-21. Retrieved 2019-08-27.
Nowick, S. M. (September 1996). "Design of a Low-Latency Asynchronous Adder Using Speculative Completion" (PDF). IEE Proceedings - Computers and Digital Techniques. 143 (5): 301–307. doi:10.1049/ip-cdt:19960704. Archived from the original (PDF) on 2021-04-22. Retrieved 2019-08-27.
Sheikh, B.; Manohar, R. (May 2010). "An Operand-Optimized Asynchronous IEEE 754 Double-Precision Floating-Point Adder" (PDF). Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems ('Async'): 151–162. Archived from the original (PDF) on 2021-04-21. Retrieved 2019-08-27.
Furber, Steve. "Principles of Asynchronous Circuit Design" (PDF). Pg. 232. Archived from the original (PDF) on 2012-04-26. Retrieved 2011-12-13.
LARD Archived March 6, 2005, at the Wayback Machine
"Seiko Epson tips flexible processor via TFT technology" Archived 2010-02-01 at the Wayback Machine by Mark LaPedus 2005
"SyNAPSE program develops advanced brain-inspired chip" Archived 2014-08-10 at the Wayback Machine. August 07, 2014.
"Серия 587 - Collection ex-USSR Chip's". Archived from the original on 2015-07-17. Retrieved 2015-07-16.
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wikidata.org

Smith, Scott C.; Di, Jia (2009). Designing Asynchronous Circuits using NULL Conventional Logic (NCL) (PDF). Synthesis Lectures on Digital Circuits & Systems. Morgan & Claypool Publishers [d]. pp. 61–73. eISSN 1932-3174. ISBN 978-1-59829-981-6. ISSN 1932-3166. Lecture #23. Retrieved 2023-09-10; Smith, Scott C.; Di, Jia (2022) [2009-07-23]. Designing Asynchronous Circuits using NULL Conventional Logic (NCL). Synthesis Lectures on Digital Circuits & Systems. University of Arkansas, Arkansas, USA: Springer Nature Switzerland AG. doi:10.1007/978-3-031-79800-9. eISSN 1932-3174. ISBN 978-3-031-79799-6. ISSN 1932-3166. Lecture #23. Retrieved 2023-09-10. (x+86+6 pages)

wiley.com

Fant, Karl M. (August 2007). Computer Science Reconsidered: The Invocation Model of Process Expression (1 ed.). Hoboken, New Jersey, USA: Wiley-Interscience / John Wiley and Sons, Inc. ISBN 978-0-471-79814-9. LCCN 2006052821. Retrieved 2023-07-23. (xix+1+269 pages)

workcraft.org

"start - Workcraft". workcraft.org. Retrieved 2021-07-28.

worldcat.org

search.worldcat.org

Staunstrup, Jørgen (1994). A Formal Approach to Hardware Design. Boston, Massachusetts, USA: Springer USA. ISBN 978-1-4615-2764-0. OCLC 852790160.
Myers, Chris J. (2001). Asynchronous circuit design. New York: J. Wiley & Sons. ISBN 0-471-46412-0. OCLC 53227301.
Vasyukevich, Vadim O. (April 2007). "Decoding asynchronous sequences". Automatic Control and Computer Sciences. 41 (2). Allerton Press: 93–99. doi:10.3103/S0146411607020058. ISSN 1558-108X. S2CID 21204394.
Vasyukevich, Vadim O. (2011). Written at Riga, Latvia. Asynchronous Operators of Sequential Logic: Venjunction & Sequention — Digital Circuits Analysis and Design. Lecture Notes in Electrical Engineering. Vol. 101 (1st ed.). Berlin / Heidelberg, Germany: Springer-Verlag. doi:10.1007/978-3-642-21611-4. ISBN 978-3-642-21610-7. ISSN 1876-1100. LCCN 2011929655. (xiii+1+123+7 pages) (NB. The back cover of this book erroneously states volume 4, whereas it actually is volume 101.)
Smith, Scott C.; Di, Jia (2009). Designing Asynchronous Circuits using NULL Conventional Logic (NCL) (PDF). Synthesis Lectures on Digital Circuits & Systems. Morgan & Claypool Publishers [d]. pp. 61–73. eISSN 1932-3174. ISBN 978-1-59829-981-6. ISSN 1932-3166. Lecture #23. Retrieved 2023-09-10; Smith, Scott C.; Di, Jia (2022) [2009-07-23]. Designing Asynchronous Circuits using NULL Conventional Logic (NCL). Synthesis Lectures on Digital Circuits & Systems. University of Arkansas, Arkansas, USA: Springer Nature Switzerland AG. doi:10.1007/978-3-031-79800-9. eISSN 1932-3174. ISBN 978-3-031-79799-6. ISSN 1932-3166. Lecture #23. Retrieved 2023-09-10. (x+86+6 pages)
Chu, T.-A. (1986-06-01). "On the models for designing VLSI asynchronous digital systems". Integration. 4 (2): 99–113. doi:10.1016/S0167-9260(86)80002-5. ISSN 0167-9260.
Yakovlev, Alexandre; Lavagno, Luciano; Sangiovanni-Vincentelli, Alberto (1996-11-01). "A unified signal transition graph model for asynchronous control circuit synthesis". Formal Methods in System Design. 9 (3): 139–188. doi:10.1007/BF00122081. ISSN 1572-8102. S2CID 26970846.
Sasao, Tsutomu (1993). Logic Synthesis and Optimization. Boston, Massachusetts, USA: Springer USA. ISBN 978-1-4615-3154-8. OCLC 852788081.
Martin, A. J.; Nystrom, M.; Wong, C. G. (November 2003). "Three generations of asynchronous microprocessors". IEEE Design & Test of Computers. 20 (6): 9–17. doi:10.1109/MDT.2003.1246159. ISSN 0740-7475. S2CID 15164301.

worldcat.org

Staunstrup, Jørgen (1994). A Formal Approach to Hardware Design. Boston, Massachusetts, USA: Springer USA. ISBN 978-1-4615-2764-0. OCLC 852790160.
Myers, Chris J. (2001). Asynchronous circuit design. New York: J. Wiley & Sons. ISBN 0-471-46412-0. OCLC 53227301.
Sasao, Tsutomu (1993). Logic Synthesis and Optimization. Boston, Massachusetts, USA: Springer USA. ISBN 978-1-4615-3154-8. OCLC 852788081.