Front end of line (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Front end of line" in English language version.

refsWebsite

Global rank English rank

2^nd place

2^nd place

1books.google.com

3^rd place

3^rd place

low place

low place

3,951^st place

2,391^st place

274^th place

309^th place

1semanticscholar.org

11^th place

8^th place

2,912^th place

6,319^th place

books.google.com

Karen A. Reinhardt and Werner Kern (2008). Handbook of Silicon Wafer Cleaning Technology (2nd ed.). William Andrew. p. 202. ISBN 978-0-8155-1554-8.

doi.org

J. Lienig, J. Scheible (2020). "Chap. 2.9.3: FEOL: Creating Devices". Fundamentals of Layout Design for Electronic Circuits. Springer. pp. 78–82. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. S2CID 215840278.
Newton, Lewis; Thanki, Aditi; Bermudez, Carlos; Artigas, Roger; Thompson, Adam; Haitjema, Han; Leach, Richard (2019). "Optimisation of Imaging Confocal Microscopy for Topography Measurements of Metal Additive Surfaces". Journal of Manufacturing and Materials Processing. 3 (2): 11. doi:10.3390/jmmp3020011 (inactive 3 June 2025).{{cite journal}}: CS1 maint: DOI inactive as of June 2025 (link)
Kim, Eun-Soo; Choi, Woo-June (2021). "In Situ Metrology for Pad Surface Monitoring in CMP Using a Common-Path Phase-Shifting Interferometry: A Feasibility Study". Applied Sciences. 11 (15): 6839. doi:10.3390/app11156839.

mdpi.com

Newton, Lewis; Thanki, Aditi; Bermudez, Carlos; Artigas, Roger; Thompson, Adam; Haitjema, Han; Leach, Richard (2019). "Optimisation of Imaging Confocal Microscopy for Topography Measurements of Metal Additive Surfaces". Journal of Manufacturing and Materials Processing. 3 (2): 11. doi:10.3390/jmmp3020011 (inactive 3 June 2025).{{cite journal}}: CS1 maint: DOI inactive as of June 2025 (link)

semanticscholar.org

api.semanticscholar.org

J. Lienig, J. Scheible (2020). "Chap. 2.9.3: FEOL: Creating Devices". Fundamentals of Layout Design for Electronic Circuits. Springer. pp. 78–82. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. S2CID 215840278.

springer.com

link.springer.com

J. Lienig, J. Scheible (2020). "Chap. 2.9.3: FEOL: Creating Devices". Fundamentals of Layout Design for Electronic Circuits. Springer. pp. 78–82. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. S2CID 215840278.

substack.com

deepforest.substack.com

Ramsundar, Bharath (26 February 2021). "A Deep Dive into Chip Manufacturing: Front End of Line (FEOL) Basics". deepforest.substack.com. Retrieved 2022-09-27.

usjpc.com

"FEOL (Front End of Line: substrate process, the first half of wafer processing) 1. Isolation | USJC：United Semiconductor Japan Co., Ltd". USJC：United Semiconductor Japan Co., Ltd. | 三重県桑名市の300mm半導体ウェーハ工場を製造拠点にしたファウンドリ専業メーカーです。超低消費電力、不揮発メモリなど先進テクノロジーを世界中のお客様に提供しています。 (in Japanese). 2019-02-22. Retrieved 2022-09-27.