Hardware acceleration (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Hardware acceleration" in English language version.

refsWebsite

Global rank English rank

7doi.org

2^nd place

4worldcat.org

5^th place

3web.archive.org

1^st place

3semanticscholar.org

11^th place

8^th place

2ieee.org

652^nd place

515^th place

2microsoft.com

153^rd place

151^st place

1wired.com

193^rd place

152^nd place

1embedded.com

low place

1researchgate.net

120^th place

125^th place

1harvard.edu

18^th place

17^th place

1enterprisetech.com

low place

1xilinx.com

low place

1design-reuse.com

low place

1optusnet.com.au

low place

1fastcompany.com

1,040^th place

623^rd place

1ecnmag.com

low place

1arxiv.org

69^th place

59^th place

1wellho.net

low place

1intel.com

1,118^th place

825^th place

1academia.edu

121^st place

142^nd place

academia.edu

Farabet, Clément, et al. "Hardware accelerated convolutional neural networks for synthetic vision systems^{[dead link]}." Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on. IEEE, 2010.

arxiv.org

Kienle, Frank; Wehn, Norbert; Meyr, Heinrich (December 2011). "On Complexity, Energy- and Implementation-Efficiency of Channel Decoders". IEEE Transactions on Communications. 59 (12): 3301–3310. arXiv:1003.3792. doi:10.1109/tcomm.2011.092011.100157. ISSN 0090-6778. S2CID 13863870.

design-reuse.com

Zhoukun WANG and Omar HAMMAMI. "A 24 Processors System on Chip FPGA Design with Network on Chip". [1]

doi.org

Sinan, Kufeoglu; Mahmut, Ozkuran (2019). "Figure 5. CPU, GPU, FPGA, and ASIC minimum energy consumption between difficulty recalculation.". Energy Consumption of Bitcoin Mining. doi:10.17863/CAM.41230.
Kim, Yeongmin; Kong, Joonho; Munir, Arslan (2020). "CPU-Accelerator Co-Scheduling for CNN Acceleration at the Edge". IEEE Access. 8: 211422–211433. Bibcode:2020IEEEA...8u1422K. doi:10.1109/ACCESS.2020.3039278. ISSN 2169-3536.
Lin, Yibo; Jiang, Zixuan; Gu, Jiaqi; Li, Wuxi; Dhar, Shounak; Ren, Haoxing; Khailany, Brucek; Pan, David Z. (April 2021). "DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 40 (4): 748–761. doi:10.1109/TCAD.2020.3003843. ISSN 1937-4151. S2CID 225744481.
Lyakhov, Pavel; Valueva, Maria; Valuev, Georgii; Nagornov, Nikolai (2020-12-18). "A Method of Increasing Digital Filter Performance Based on Truncated Multiply-Accumulate Units". Applied Sciences. 10 (24): 9052. doi:10.3390/app10249052. ISSN 2076-3417. Hardware simulation on FPGA increased the digital filter performance.
Mohan, Prashanth; Wang, Wen; Jungk, Bernhard; Niederhagen, Ruben; Szefer, Jakub; Mai, Ken (October 2020). "ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS". 2020 IEEE 38th International Conference on Computer Design (ICCD). Hartford, CT, USA: IEEE. pp. 656–662. doi:10.1109/ICCD50377.2020.00112. ISBN 978-1-7281-9710-4. S2CID 229330964.
Vassányi, István (1998). "Implementing processor arrays on FPGAs". Field-Programmable Logic and Applications from FPGAs to Computing Paradigm. Lecture Notes in Computer Science. Vol. 1482. pp. 446–450. doi:10.1007/BFb0055278. ISBN 978-3-540-64948-9.
Kienle, Frank; Wehn, Norbert; Meyr, Heinrich (December 2011). "On Complexity, Energy- and Implementation-Efficiency of Channel Decoders". IEEE Transactions on Communications. 59 (12): 3301–3310. arXiv:1003.3792. doi:10.1109/tcomm.2011.092011.100157. ISSN 0090-6778. S2CID 13863870.

ecnmag.com

"Scientists Squeeze Over 1,000 Cores onto One Chip". 2011. [3] Archived 2012-03-05 at the Wayback Machine

embedded.com

"Embedded". Archived from the original on 2007-10-08. Retrieved 2012-08-18. "FPGA Architectures from 'A' to 'Z'" by Clive Maxfield 2006

enterprisetech.com

Morgan, Timothy Pricket (2014-09-03). "How Microsoft Is Using FPGAs To Speed Up Bing Search". Enterprise Tech. Retrieved 2018-09-18.

fastcompany.com

Kit Eaton. "1,000 Core CPU Achieved: Your Future Desktop Will Be a Supercomputer". 2011. [2]

harvard.edu

ui.adsabs.harvard.edu

Kim, Yeongmin; Kong, Joonho; Munir, Arslan (2020). "CPU-Accelerator Co-Scheduling for CNN Acceleration at the Edge". IEEE Access. 8: 211422–211433. Bibcode:2020IEEEA...8u1422K. doi:10.1109/ACCESS.2020.3039278. ISSN 2169-3536.

ieee.org

ieeexplore.ieee.org

Lin, Yibo; Jiang, Zixuan; Gu, Jiaqi; Li, Wuxi; Dhar, Shounak; Ren, Haoxing; Khailany, Brucek; Pan, David Z. (April 2021). "DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 40 (4): 748–761. doi:10.1109/TCAD.2020.3003843. ISSN 1937-4151. S2CID 225744481.
Mohan, Prashanth; Wang, Wen; Jungk, Bernhard; Niederhagen, Ruben; Szefer, Jakub; Mai, Ken (October 2020). "ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS". 2020 IEEE 38th International Conference on Computer Design (ICCD). Hartford, CT, USA: IEEE. pp. 656–662. doi:10.1109/ICCD50377.2020.00112. ISBN 978-1-7281-9710-4. S2CID 229330964.

intel.com

https://www.intel.com/content/dam/doc/product-brief/intel-pro-100-s-desktop-adapter-datasheet.pdf ^{[bare URL PDF]}

microsoft.com

"Project Catapult". Microsoft Research.
"Compression Accelerators - Microsoft Research". Microsoft Research. Retrieved 2017-10-07.

optusnet.com.au

members.optusnet.com.au

John Kent. "Micro16 Array - A Simple CPU Array"

researchgate.net

Sinan, Kufeoglu; Mahmut, Ozkuran (2019). "Figure 5. CPU, GPU, FPGA, and ASIC minimum energy consumption between difficulty recalculation.". Energy Consumption of Bitcoin Mining. doi:10.17863/CAM.41230.

semanticscholar.org

api.semanticscholar.org

Lin, Yibo; Jiang, Zixuan; Gu, Jiaqi; Li, Wuxi; Dhar, Shounak; Ren, Haoxing; Khailany, Brucek; Pan, David Z. (April 2021). "DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 40 (4): 748–761. doi:10.1109/TCAD.2020.3003843. ISSN 1937-4151. S2CID 225744481.
Mohan, Prashanth; Wang, Wen; Jungk, Bernhard; Niederhagen, Ruben; Szefer, Jakub; Mai, Ken (October 2020). "ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS". 2020 IEEE 38th International Conference on Computer Design (ICCD). Hartford, CT, USA: IEEE. pp. 656–662. doi:10.1109/ICCD50377.2020.00112. ISBN 978-1-7281-9710-4. S2CID 229330964.
Kienle, Frank; Wehn, Norbert; Meyr, Heinrich (December 2011). "On Complexity, Energy- and Implementation-Efficiency of Channel Decoders". IEEE Transactions on Communications. 59 (12): 3301–3310. arXiv:1003.3792. doi:10.1109/tcomm.2011.092011.100157. ISSN 0090-6778. S2CID 13863870.

web.archive.org

"Embedded". Archived from the original on 2007-10-08. Retrieved 2012-08-18. "FPGA Architectures from 'A' to 'Z'" by Clive Maxfield 2006
MicroBlaze Soft Processor: Frequently Asked Questions Archived 2011-10-27 at the Wayback Machine
"Scientists Squeeze Over 1,000 Cores onto One Chip". 2011. [3] Archived 2012-03-05 at the Wayback Machine

wellho.net

"Regular Expressions in hardware". Retrieved 17 July 2014.

wired.com

"Microsoft Supercharges Bing Search With Programmable Chips". WIRED. 16 June 2014.

worldcat.org

search.worldcat.org

Kim, Yeongmin; Kong, Joonho; Munir, Arslan (2020). "CPU-Accelerator Co-Scheduling for CNN Acceleration at the Edge". IEEE Access. 8: 211422–211433. Bibcode:2020IEEEA...8u1422K. doi:10.1109/ACCESS.2020.3039278. ISSN 2169-3536.
Lin, Yibo; Jiang, Zixuan; Gu, Jiaqi; Li, Wuxi; Dhar, Shounak; Ren, Haoxing; Khailany, Brucek; Pan, David Z. (April 2021). "DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 40 (4): 748–761. doi:10.1109/TCAD.2020.3003843. ISSN 1937-4151. S2CID 225744481.
Lyakhov, Pavel; Valueva, Maria; Valuev, Georgii; Nagornov, Nikolai (2020-12-18). "A Method of Increasing Digital Filter Performance Based on Truncated Multiply-Accumulate Units". Applied Sciences. 10 (24): 9052. doi:10.3390/app10249052. ISSN 2076-3417. Hardware simulation on FPGA increased the digital filter performance.
Kienle, Frank; Wehn, Norbert; Meyr, Heinrich (December 2011). "On Complexity, Energy- and Implementation-Efficiency of Channel Decoders". IEEE Transactions on Communications. 59 (12): 3301–3310. arXiv:1003.3792. doi:10.1109/tcomm.2011.092011.100157. ISSN 0090-6778. S2CID 13863870.

xilinx.com

MicroBlaze Soft Processor: Frequently Asked Questions Archived 2011-10-27 at the Wayback Machine