Intel 5-level paging (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Intel 5-level paging" in English language version.

refsWebsite

Global rank English rank

2intel.com

1,118^th place

825^th place

2amd.com

2,816^th place

2,038^th place

1anandtech.com

1,383^rd place

878^th place

1microsoft.com

153^rd place

151^st place

1espacenet.com

800^th place

676^th place

1doi.org

2^nd place

1worldcat.org

5^th place

1arm.com

4,773^rd place

3,130^th place

1washington.edu

1,067^th place

749^th place

1github.com

383^rd place

320^th place

1zdnet.com

786^th place

558^th place

1phoronix.com

4,683^rd place

3,096^th place

1iu.edu

3,316^th place

1,982^nd place

1kernel.org

4,558^th place

3,044^th place

1lwn.net

4,423^rd place

2,925^th place

1x.com

low place

amd.com

"Tuning Guide for AMD EPYC™ 9004 Processors" (PDF). AMD. September 2023.
"4TH GEN AMD EPYC™ PROCESSOR ARCHITECTURE" (PDF). AMD. May 2024.

anandtech.com

Cutress, Ian. "Sunny Cove Microarchitecture: A Peek At the Back End". Intel's Architecture Day 2018: The Future of Core, Intel GPUs, 10nm, and Hybrid x86. Retrieved 15 October 2019.

arm.com

infocenter.arm.com

"ARM Information Center". infocenter.arm.com. Retrieved 26 April 2018.

doi.org

"CSALT: Context Switch Aware Large TLB". MICRO-50: the 50th Annual IEEE/ACM International Symposium on Microarchitecture : proceedings. Cambridge, MA: Institute of Electrical and Electronics Engineers., IEEE Computer Society., ACM Special Interest Group on Microprogramming. 14 October 2017. p. 450. doi:10.1145/3123939.3124549. ISBN 978-1-4503-4952-9. OCLC 1032337814.

espacenet.com

worldwide.espacenet.com

US patent 9858198, Larry Seiler, "64KB page system that supports 4KB page operation", published 2016-12-29, issued 2018-01-02, assigned to Intel Corp.

github.com

"CPUID dump for 96-Core AMD Ryzen Threadripper PRO 7995WX (Storm Peak) Zen4". GitHub. 19 October 2023.

intel.com

"5-Level Paging and 5-Level EPT". Intel Corporation. May 2017.
Intel® 64 and IA-32 Architectures Software Developer's Manual. Vol. 3A. Intel Corporation.

iu.edu

lkml.iu.edu

Shutemov, Kirill A. (8 December 2016). "[RFC, PATCHv1 00/28] 5-level paging". Linux kernel mailing list (Mailing list). Retrieved 26 April 2018.

kernel.org

"Page Table Management". www.kernel.org. Retrieved 26 April 2018.

lwn.net

"Four-level page tables [LWN.net]". lwn.net. 12 October 2004. Retrieved 26 April 2018.

microsoft.com

learn.microsoft.com

Hudek, Ted (June 2017). "Operating Systems and PAE Support - Windows 10 hardware dev". Microsoft Learn. Retrieved 27 January 2024.

phoronix.com

Michael Larabel (9 December 2016). "Intel Working On 5-Level Paging To Increase Linux Virtual/Physical Address Space - Phoronix". Phoronix. Retrieved 26 April 2018.

washington.edu

courses.cs.washington.edu

Levy, Hank (Autumn 2008). "CSE 451: Operating Systems: Paging & TLBs" (PDF). University of Washington. Retrieved 26 April 2018.

worldcat.org

search.worldcat.org

"CSALT: Context Switch Aware Large TLB". MICRO-50: the 50th Annual IEEE/ACM International Symposium on Microarchitecture : proceedings. Cambridge, MA: Institute of Electrical and Electronics Engineers., IEEE Computer Society., ACM Special Interest Group on Microprogramming. 14 October 2017. p. 450. doi:10.1145/3123939.3124549. ISBN 978-1-4503-4952-9. OCLC 1032337814.

x.com

@aionescu (23 June 2019). "Old farts like me will remember the days of ntoskrnl.exe, ntkrnlpa.exe, ntkrnlmp.exe and ntkrpamp.exe" (Tweet) – via Twitter.

zdnet.com

Tung, Liam. "First Linux 4.14 release adds "very core" features, arrives in time for kernel's 26th birthday". ZDNet. Retrieved 25 April 2018.