Multiple patterning (English Wikipedia)

Duan, Huigao; Winston, Donald; Yang, Joel K. W.; Cord, Bryan M.; Manfrinato, Vitor R.; Berggren, Karl K. (November 2010). "Sub-10-nm half-pitch electron-beam lithography by using poly(methyl methacrylate) as a negative resist" (PDF). Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena. 28 (6): C6C58–C6C62. Bibcode:2010JVSTB..28C..58D. doi:10.1116/1.3501353. hdl:1721.1/73447. Archived from the original (PDF) on 2012-01-19.
D. C. Flanders; N. N. Efremow (1983). "Generation of <50 nm period gratings using edge defined techniques". Journal of Vacuum Science & Technology B. 1 (4): 1105–1108. Bibcode:1983JVSTB...1.1105F. doi:10.1116/1.582643.
Chris Bencher; Yongmei Chen; Huixiong Dai; Warren Montgomery; Lior Huli (2008). "22nm half-pitch patterning by CVD spacer self alignment double patterning (SADP)". Optical Microlithography XXI. 6924. Optical Microlithography XXI; 69244E: 69244E. Bibcode:2008SPIE.6924E..4EB. doi:10.1117/12.772953. S2CID 121968664.
A. Vanleenhove; D. Van Steenwinckel (2007). Flagello, Donis G (ed.). "A litho-only approach to double patterning". Society of Photo-Optical Instrumentation Engineers (Spie) Conference Series. Optical Microlithography XX. 6520. Optical Microlithography XX; 65202F: 65202F. Bibcode:2007SPIE.6520E..2FV. doi:10.1117/12.713914. S2CID 119829809.
De Simone, Danilo; Vandenberghe, Geert (2019). "Printability study of EUV double patterning for CMOS metal layers". In Goldberg, Kenneth A. (ed.). Extreme Ultraviolet (EUV) Lithography X. p. 21. doi:10.1117/12.2515603. ISBN 978-1-5106-2561-7.
Milan Vala; Jiri Homola (2014). "Flexible method based on four-beam interference lithography for fabrication of large areas of perfectly periodic plasmonic arrays". Optics Express. 22 (15): 18778–18789. Bibcode:2014OExpr..2218778V. doi:10.1364/OE.22.018778. PMID 25089495.
van Setten, Eelco; Wittebrood, Friso; et al. (September 4, 2015). "Patterning options for N7 logic: Prospects and challenges for EUV". In Behringer, Uwe F.W; Finders, Jo (eds.). 31st European Mask and Lithography Conference. Vol. 9661. pp. 96610G. Bibcode:2015SPIE.9661E..0GV. doi:10.1117/12.2196426. S2CID 106609033.
Kim, Ryoung-Han; Wood, Obert; Crouse, Michael; Chen, Yulu; Plachecki, Vince; Hsu, Stephen; Gronlund, Keith (2016). "Application of EUV resolution enhancement techniques (RET) to optimize and extend single exposure bi-directional patterning for 7nm and beyond logic designs". In Panning, Eric M.; Goldberg, Kenneth A. (eds.). Extreme Ultraviolet (EUV) Lithography VII. Vol. 9776. pp. 97761R. doi:10.1117/12.2219177.
Chao, Robin; Kohli, Kriti K.; Zhang, Yunlin; Madan, Anita; Muthinti, Gangadhara Raja; Hong, Augustin J.; Conklin, David; Holt, Judson; Bailey, Todd C. (2014-01-01). "Multitechnique metrology methods for evaluating pitch walking in 14 nm and beyond FinFETs". Journal of Micro/Nanolithography, MEMS, and MOEMS. 13 (4): 041411. Bibcode:2014JMM&M..13d1411C. doi:10.1117/1.JMM.13.4.041411. ISSN 1932-5150. S2CID 122374784.
Raley, Angélique; Thibaut, Sophie; Mohanty, Nihar; Subhadeep, Kal; Nakamura, Satoru; Ko, Akiteru; O'Meara, David; Tapily, Kandabara; Consiglio, Steve; Biolsi, Peter (2016). "Self-aligned quadruple patterning integration using spacer on spacer pitch splitting at the resist level for sub-32nm pitch applications". In Lin, Qinghuang; Engelmann, Sebastian U. (eds.). Advanced Etch Technology for Nanopatterning V. Vol. 9782. pp. 97820F. doi:10.1117/12.2219321.

eetimes.com

LaPedus, Mark (March 13, 2008). "JSR demos 'freezing material' for 22-nm production". Archived from the original on 2014-07-15.
Merritt, Rick (October 7, 2015). "5nm Test Lights Litho Path Hybrid 193i, EUV seen as best approach". EETimes.
Intel unveils 10nm
TSMC on 2017
EUV Errors Under Attack

embedded.com

Hynix M1X NAND

ernet.in

ece.iisc.ernet.in

Intel Technology Journal 45nm issue

euvlitho.com

Y. Borodovsky (2012). EUV Lithography at Insertion and Beyond (PDF). International Workshop on EUV Lithography.
ASML High-NA EUV

extremetech.com

Intel goes to 7nm without EUV

handle.net

hdl.handle.net

Duan, Huigao; Winston, Donald; Yang, Joel K. W.; Cord, Bryan M.; Manfrinato, Vitor R.; Berggren, Karl K. (November 2010). "Sub-10-nm half-pitch electron-beam lithography by using poly(methyl methacrylate) as a negative resist" (PDF). Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena. 28 (6): C6C58–C6C62. Bibcode:2010JVSTB..28C..58D. doi:10.1116/1.3501353. hdl:1721.1/73447. Archived from the original (PDF) on 2012-01-19.

harvard.edu

ui.adsabs.harvard.edu

Duan, Huigao; Winston, Donald; Yang, Joel K. W.; Cord, Bryan M.; Manfrinato, Vitor R.; Berggren, Karl K. (November 2010). "Sub-10-nm half-pitch electron-beam lithography by using poly(methyl methacrylate) as a negative resist" (PDF). Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena. 28 (6): C6C58–C6C62. Bibcode:2010JVSTB..28C..58D. doi:10.1116/1.3501353. hdl:1721.1/73447. Archived from the original (PDF) on 2012-01-19.
D. C. Flanders; N. N. Efremow (1983). "Generation of <50 nm period gratings using edge defined techniques". Journal of Vacuum Science & Technology B. 1 (4): 1105–1108. Bibcode:1983JVSTB...1.1105F. doi:10.1116/1.582643.
Chris Bencher; Yongmei Chen; Huixiong Dai; Warren Montgomery; Lior Huli (2008). "22nm half-pitch patterning by CVD spacer self alignment double patterning (SADP)". Optical Microlithography XXI. 6924. Optical Microlithography XXI; 69244E: 69244E. Bibcode:2008SPIE.6924E..4EB. doi:10.1117/12.772953. S2CID 121968664.
A. Vanleenhove; D. Van Steenwinckel (2007). Flagello, Donis G (ed.). "A litho-only approach to double patterning". Society of Photo-Optical Instrumentation Engineers (Spie) Conference Series. Optical Microlithography XX. 6520. Optical Microlithography XX; 65202F: 65202F. Bibcode:2007SPIE.6520E..2FV. doi:10.1117/12.713914. S2CID 119829809.
Milan Vala; Jiri Homola (2014). "Flexible method based on four-beam interference lithography for fabrication of large areas of perfectly periodic plasmonic arrays". Optics Express. 22 (15): 18778–18789. Bibcode:2014OExpr..2218778V. doi:10.1364/OE.22.018778. PMID 25089495.
van Setten, Eelco; Wittebrood, Friso; et al. (September 4, 2015). "Patterning options for N7 logic: Prospects and challenges for EUV". In Behringer, Uwe F.W; Finders, Jo (eds.). 31st European Mask and Lithography Conference. Vol. 9661. pp. 96610G. Bibcode:2015SPIE.9661E..0GV. doi:10.1117/12.2196426. S2CID 106609033.
Chao, Robin; Kohli, Kriti K.; Zhang, Yunlin; Madan, Anita; Muthinti, Gangadhara Raja; Hong, Augustin J.; Conklin, David; Holt, Judson; Bailey, Todd C. (2014-01-01). "Multitechnique metrology methods for evaluating pitch walking in 14 nm and beyond FinFETs". Journal of Micro/Nanolithography, MEMS, and MOEMS. 13 (4): 041411. Bibcode:2014JMM&M..13d1411C. doi:10.1117/1.JMM.13.4.041411. ISSN 1932-5150. S2CID 122374784.

ieee.org

ieeexplore.ieee.org

[1] A. Yeoh et al., IITC 2018.
[2] H. Rhee et al., 2018 Symp. VLSI Tech., 217.

ieee.org

"IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers. Archived from the original on September 9, 2018. Retrieved 4 July 2019.

imec.be

www2.imec.be

"Scaling-driven nanoelectronics - Resists". Archived from the original on 2010-03-23.

intel.com

download.intel.com

Intel 45nm HKMG

newsroom.intel.com

Intel 14 nm Leadership

knight-sac-media.com

vweb2.knight-sac-media.com

Samsung receives 24 immersion tools from ASML in 2010

linkedin.com

mentor.com

Calibre support for 8LPP and 7LPP

micron.com

"Micron Named Among Top 100 Global Innovators for Sixth Straight Year". Micron Technology. 2018-02-15. Retrieved 5 July 2019.

mit.edu

rle.mit.edu

Duan, Huigao; Winston, Donald; Yang, Joel K. W.; Cord, Bryan M.; Manfrinato, Vitor R.; Berggren, Karl K. (November 2010). "Sub-10-nm half-pitch electron-beam lithography by using poly(methyl methacrylate) as a negative resist" (PDF). Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena. 28 (6): C6C58–C6C62. Bibcode:2010JVSTB..28C..58D. doi:10.1116/1.3501353. hdl:1721.1/73447. Archived from the original (PDF) on 2012-01-19.

nih.gov

pubmed.ncbi.nlm.nih.gov

Milan Vala; Jiri Homola (2014). "Flexible method based on four-beam interference lithography for fabrication of large areas of perfectly periodic plasmonic arrays". Optics Express. 22 (15): 18778–18789. Bibcode:2014OExpr..2218778V. doi:10.1364/OE.22.018778. PMID 25089495.

nist.gov

NIST 2011 report on LER in PS-b-PMMA DSA

osti.gov

Chao, Weilun; Kim, Jihoon; Anderson, Erik H.; Fischer, Peter; Rekawa, Senajith; Attwood, David T. (2009-01-09). Double patterning HSQ processes of zone plates for 10 nm diffraction limited performance. The 53rd International Symposium on Electron, Ion, and Photon Beams and Nanolithography, Marco Island, FL, May 26–29, 2009.

psu.edu

citeseerx.ist.psu.edu

F. M. Schellenberg et al., DAC 2001,Adoption of OPC and the Impact on Design and Layout.

researchgate.net

Milan Vala; Jiri Homola (2014). "Flexible method based on four-beam interference lithography for fabrication of large areas of perfectly periodic plasmonic arrays". Optics Express. 22 (15): 18778–18789. Bibcode:2014OExpr..2218778V. doi:10.1364/OE.22.018778. PMID 25089495.

samsung.com

news.samsung.com

Samsung announces 10nm FinFET process for SoC

semanticscholar.org

api.semanticscholar.org

Chris Bencher; Yongmei Chen; Huixiong Dai; Warren Montgomery; Lior Huli (2008). "22nm half-pitch patterning by CVD spacer self alignment double patterning (SADP)". Optical Microlithography XXI. 6924. Optical Microlithography XXI; 69244E: 69244E. Bibcode:2008SPIE.6924E..4EB. doi:10.1117/12.772953. S2CID 121968664.
A. Vanleenhove; D. Van Steenwinckel (2007). Flagello, Donis G (ed.). "A litho-only approach to double patterning". Society of Photo-Optical Instrumentation Engineers (Spie) Conference Series. Optical Microlithography XX. 6520. Optical Microlithography XX; 65202F: 65202F. Bibcode:2007SPIE.6520E..2FV. doi:10.1117/12.713914. S2CID 119829809.
van Setten, Eelco; Wittebrood, Friso; et al. (September 4, 2015). "Patterning options for N7 logic: Prospects and challenges for EUV". In Behringer, Uwe F.W; Finders, Jo (eds.). 31st European Mask and Lithography Conference. Vol. 9661. pp. 96610G. Bibcode:2015SPIE.9661E..0GV. doi:10.1117/12.2196426. S2CID 106609033.
Chao, Robin; Kohli, Kriti K.; Zhang, Yunlin; Madan, Anita; Muthinti, Gangadhara Raja; Hong, Augustin J.; Conklin, David; Holt, Judson; Bailey, Todd C. (2014-01-01). "Multitechnique metrology methods for evaluating pitch walking in 14 nm and beyond FinFETs". Journal of Micro/Nanolithography, MEMS, and MOEMS. 13 (4): 041411. Bibcode:2014JMM&M..13d1411C. doi:10.1117/1.JMM.13.4.041411. ISSN 1932-5150. S2CID 122374784.

semiconwest.org

Synopsis Presentation at Semicon West 2013 Archived 2015-09-24 at the Wayback Machine

semiengineering.com

Intel discusses 10nm
"The Bumpy Road to 10nm FinFETs". 21 May 2015.

semimd.com

"Semimd - Health & Fitness Magazine 2020". 10 November 2023.
IEDM 2016 Setting Stage for 7/5 nm

spie.org

SAQP for FinFETs

staticasml.com

Extending immersion lithography to 1xnm nodes

synopsys.com

Triple patterning is becoming common at 10nm

techinsights.com

Samsung 18 nm DRAM

tedvc.com

Samsung 80nm DRAM

tsmc.com

wccftech.com

NVIDIA Pascal Tesla P100 Unveiled - 15.3 Billion Transistors on a 610mm2 16nm Die

web.archive.org

Duan, Huigao; Winston, Donald; Yang, Joel K. W.; Cord, Bryan M.; Manfrinato, Vitor R.; Berggren, Karl K. (November 2010). "Sub-10-nm half-pitch electron-beam lithography by using poly(methyl methacrylate) as a negative resist" (PDF). Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena. 28 (6): C6C58–C6C62. Bibcode:2010JVSTB..28C..58D. doi:10.1116/1.3501353. hdl:1721.1/73447. Archived from the original (PDF) on 2012-01-19.
"IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers. Archived from the original on September 9, 2018. Retrieved 4 July 2019.
"Scaling-driven nanoelectronics - Resists". Archived from the original on 2010-03-23.
LaPedus, Mark (March 13, 2008). "JSR demos 'freezing material' for 22-nm production". Archived from the original on 2014-07-15.
Synopsis Presentation at Semicon West 2013 Archived 2015-09-24 at the Wayback Machine

wikichip.org

en.wikichip.org

"14 nm lithography process - WikiChip".

worldcat.org

search.worldcat.org

Chao, Robin; Kohli, Kriti K.; Zhang, Yunlin; Madan, Anita; Muthinti, Gangadhara Raja; Hong, Augustin J.; Conklin, David; Holt, Judson; Bailey, Todd C. (2014-01-01). "Multitechnique metrology methods for evaluating pitch walking in 14 nm and beyond FinFETs". Journal of Micro/Nanolithography, MEMS, and MOEMS. 13 (4): 041411. Bibcode:2014JMM&M..13d1411C. doi:10.1117/1.JMM.13.4.041411. ISSN 1932-5150. S2CID 122374784.