Teraflops Research Chip (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Teraflops Research Chip" in English language version.

refsWebsite

Global rank English rank

4doi.org

2^nd place

4intel.com

1,118^th place

825^th place

3web.archive.org

1^st place

3ieee.org

652^nd place

515^th place

3semanticscholar.org

11^th place

8^th place

2harvard.edu

18^th place

17^th place

1springer.com

274^th place

309^th place

1worldcat.org

5^th place

1wikichip.org

low place

8,965^th place

doi.org

Vangal, Sriram; Howard, Jason; Ruhl, Gregory; Dighe, Saurabh; Wilson, Howard; Tschanz, James; Finan, David; Iyer, Priya; Singh, Arvind; Jacob, Tiju; Jain, Shailendra (2007). "An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS". 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. pp. 98–589. doi:10.1109/ISSCC.2007.373606. ISBN 978-1-4244-0852-8. S2CID 20065641.
Peh, Li-Shiuan; Keckler, Stephen W.; Vangal, Sriram (2009), Keckler, Stephen W.; Olukotun, Kunle; Hofstee, H. Peter (eds.), "On-Chip Networks for Multicore Systems", Multicore Processors and Systems, Springer US, pp. 35–71, Bibcode:2009mps..book...35P, doi:10.1007/978-1-4419-0263-4_2, ISBN 978-1-4419-0262-7, retrieved 2020-05-14
Vangal, S.R.; Howard, J.; Ruhl, G.; Dighe, S.; Wilson, H.; Tschanz, J.; Finan, D.; Singh, A.; Jacob, T.; Jain, S.; Erraguntla, V. (2008). "An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS". IEEE Journal of Solid-State Circuits. 43 (1): 29–41. Bibcode:2008IJSSC..43...29V. doi:10.1109/JSSC.2007.910957. ISSN 0018-9200. S2CID 15672087.
Bautista, Jerry (2008). Tera-scale computing and interconnect challenges - 3D stacking considerations. 2008 IEEE Hot Chips 20 Symposium (HCS). Stanford, CA, USA: IEEE. pp. 1–34. doi:10.1109/HOTCHIPS.2008.7476514. ISBN 978-1-4673-8871-9. S2CID 26400101.

harvard.edu

ui.adsabs.harvard.edu

Peh, Li-Shiuan; Keckler, Stephen W.; Vangal, Sriram (2009), Keckler, Stephen W.; Olukotun, Kunle; Hofstee, H. Peter (eds.), "On-Chip Networks for Multicore Systems", Multicore Processors and Systems, Springer US, pp. 35–71, Bibcode:2009mps..book...35P, doi:10.1007/978-1-4419-0263-4_2, ISBN 978-1-4419-0262-7, retrieved 2020-05-14
Vangal, S.R.; Howard, J.; Ruhl, G.; Dighe, S.; Wilson, H.; Tschanz, J.; Finan, D.; Singh, A.; Jacob, T.; Jain, S.; Erraguntla, V. (2008). "An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS". IEEE Journal of Solid-State Circuits. 43 (1): 29–41. Bibcode:2008IJSSC..43...29V. doi:10.1109/JSSC.2007.910957. ISSN 0018-9200. S2CID 15672087.

ieee.org

ieeexplore.ieee.org

Vangal, Sriram; Howard, Jason; Ruhl, Gregory; Dighe, Saurabh; Wilson, Howard; Tschanz, James; Finan, David; Iyer, Priya; Singh, Arvind; Jacob, Tiju; Jain, Shailendra (2007). "An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS". 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. pp. 98–589. doi:10.1109/ISSCC.2007.373606. ISBN 978-1-4244-0852-8. S2CID 20065641.
Vangal, S.R.; Howard, J.; Ruhl, G.; Dighe, S.; Wilson, H.; Tschanz, J.; Finan, D.; Singh, A.; Jacob, T.; Jain, S.; Erraguntla, V. (2008). "An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS". IEEE Journal of Solid-State Circuits. 43 (1): 29–41. Bibcode:2008IJSSC..43...29V. doi:10.1109/JSSC.2007.910957. ISSN 0018-9200. S2CID 15672087.
Bautista, Jerry (2008). Tera-scale computing and interconnect challenges - 3D stacking considerations. 2008 IEEE Hot Chips 20 Symposium (HCS). Stanford, CA, USA: IEEE. pp. 1–34. doi:10.1109/HOTCHIPS.2008.7476514. ISBN 978-1-4673-8871-9. S2CID 26400101.

intel.com

"Intel Develops Tera-Scale Research Chips". Intel News Release. 2006.
Intel Corporation (February 11, 2007). "Intel Research Advances 'Era Of Tera'". Intel Press Room. Archived from the original on April 13, 2009.

techresearch.intel.com

Intel Corporation. "Teraflops Research Chip". Archived from the original on July 22, 2010.

download.intel.com

Intel's Teraflops Research Chip (PDF). Intel Corporation. 2007. Archived from the original (PDF) on February 18, 2020.

semanticscholar.org

api.semanticscholar.org

Vangal, Sriram; Howard, Jason; Ruhl, Gregory; Dighe, Saurabh; Wilson, Howard; Tschanz, James; Finan, David; Iyer, Priya; Singh, Arvind; Jacob, Tiju; Jain, Shailendra (2007). "An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS". 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. pp. 98–589. doi:10.1109/ISSCC.2007.373606. ISBN 978-1-4244-0852-8. S2CID 20065641.
Vangal, S.R.; Howard, J.; Ruhl, G.; Dighe, S.; Wilson, H.; Tschanz, J.; Finan, D.; Singh, A.; Jacob, T.; Jain, S.; Erraguntla, V. (2008). "An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS". IEEE Journal of Solid-State Circuits. 43 (1): 29–41. Bibcode:2008IJSSC..43...29V. doi:10.1109/JSSC.2007.910957. ISSN 0018-9200. S2CID 15672087.
Bautista, Jerry (2008). Tera-scale computing and interconnect challenges - 3D stacking considerations. 2008 IEEE Hot Chips 20 Symposium (HCS). Stanford, CA, USA: IEEE. pp. 1–34. doi:10.1109/HOTCHIPS.2008.7476514. ISBN 978-1-4673-8871-9. S2CID 26400101.

springer.com

link.springer.com

Peh, Li-Shiuan; Keckler, Stephen W.; Vangal, Sriram (2009), Keckler, Stephen W.; Olukotun, Kunle; Hofstee, H. Peter (eds.), "On-Chip Networks for Multicore Systems", Multicore Processors and Systems, Springer US, pp. 35–71, Bibcode:2009mps..book...35P, doi:10.1007/978-1-4419-0263-4_2, ISBN 978-1-4419-0262-7, retrieved 2020-05-14

web.archive.org

Intel Corporation. "Teraflops Research Chip". Archived from the original on July 22, 2010.
Intel Corporation (February 11, 2007). "Intel Research Advances 'Era Of Tera'". Intel Press Room. Archived from the original on April 13, 2009.
Intel's Teraflops Research Chip (PDF). Intel Corporation. 2007. Archived from the original (PDF) on February 18, 2020.

wikichip.org

en.wikichip.org

Fossum, Tryggve (2007). High End MPSOC - The Personal Super Computer (PDF). MPSoC Conference 2007. p. 6.

worldcat.org

search.worldcat.org

Vangal, S.R.; Howard, J.; Ruhl, G.; Dighe, S.; Wilson, H.; Tschanz, J.; Finan, D.; Singh, A.; Jacob, T.; Jain, S.; Erraguntla, V. (2008). "An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS". IEEE Journal of Solid-State Circuits. 43 (1): 29–41. Bibcode:2008IJSSC..43...29V. doi:10.1109/JSSC.2007.910957. ISSN 0018-9200. S2CID 15672087.