Vector processor (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Vector processor" in English language version.

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alastairreid.github.io (Global: low place; English: low place)

archive.org (Global: 6th place; English: 6th place)

arm.com (Global: 4,773rd place; English: 3,130th place)

developer.arm.com

community.arm.com

arxiv.org (Global: 69th place; English: 59th place)

  • Moreira, José E.; Barton, Kit; Battle, Steven; Bergner, Peter; Bertran, Ramon; Bhat, Puneeth; Caldeira, Pedro; Edelsohn, David; Fossum, Gordon; Frey, Brad; Ivanovic, Nemanja; Kerchner, Chip; Lim, Vincent; Kapoor, Shakti; Tulio Machado Filho; Silvia Melitta Mueller; Olsson, Brett; Sadasivam, Satish; Saleil, Baptiste; Schmidt, Bill; Srinivasaraghavan, Rajalakshmi; Srivatsan, Shricharan; Thompto, Brian; Wagner, Andreas; Wu, Nelson (2021). "A matrix math facility for Power ISA(TM) processors". arXiv:2104.03142 [cs.AR].

bitsavers.org (Global: 4,153rd place; English: 2,291st place)

cmu.edu (Global: 1,564th place; English: 1,028th place)

course.ece.cmu.edu

doi.org (Global: 2nd place; English: 2nd place)

ed.ac.uk (Global: 1,871st place; English: 1,234th place)

inf.ed.ac.uk

ghostarchive.org (Global: 32nd place; English: 21st place)

github.com (Global: 383rd place; English: 320th place)

  • "asm-lessons/lesson_01/index.md at main · FFmpeg/asm-lessons". GitHub. Retrieved 2025-04-25.
  • MIAOW GPU
  • "Riscv-v-spec/V-spec.adoc at master · riscv/Riscv-v-spec". GitHub. 16 June 2023.
  • "Release Vector Extension 1.0, frozen for public review · riscvarchive/Riscv-v-spec". GitHub.
  • "Riscv-v-spec/V-spec.adoc at master · riscv/Riscv-v-spec". GitHub. 19 November 2022.
  • Videocore IV Programmer's Manual
  • "Riscv-v-spec/V-spec.adoc at master · riscv/Riscv-v-spec". GitHub. 19 November 2022.
  • RISC-V RVV ISA
  • RVV register gather-scatter instructions
  • LMUL > 1 in RVV
  • Videocore IV QPU
  • RVV fault-first loads
  • RVV strncpy example

globenewswire.com (Global: 2,614th place; English: 1,549th place)

handle.net (Global: 102nd place; English: 76th place)

hdl.handle.net

  • Miyaoka, Y.; Choi, J.; Togawa, N.; Yanagisawa, M.; Ohtsuki, T. (2002). An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. Asia-Pacific Conference on Circuits and Systems. Vol. 1. pp. 171–176. doi:10.1109/APCCAS.2002.1114930. hdl:2065/10689.

jbush001.github.io (Global: low place; English: low place)

lanl.gov (Global: 3,495th place; English: 2,913th place)

libre-soc.org (Global: low place; English: low place)

miaowgpu.org (Global: low place; English: low place)

nvidia.com (Global: 2,503rd place; English: 1,760th place)

docs.nvidia.com

ozlabs.org (Global: low place; English: low place)

patchwork.ozlabs.org

patents.google.com (Global: 1,182nd place; English: 725th place)

sakura.ne.jp (Global: 1,806th place; English: 1,660th place)

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springer.com (Global: 274th place; English: 309th place)

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stackoverflow.com (Global: 4,643rd place; English: 2,973rd place)

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youtube.com (Global: 9th place; English: 13th place)

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