Vector processor (English Wikipedia)

Moreira, José E.; Barton, Kit; Battle, Steven; Bergner, Peter; Bertran, Ramon; Bhat, Puneeth; Caldeira, Pedro; Edelsohn, David; Fossum, Gordon; Frey, Brad; Ivanovic, Nemanja; Kerchner, Chip; Lim, Vincent; Kapoor, Shakti; Tulio Machado Filho; Silvia Melitta Mueller; Olsson, Brett; Sadasivam, Satish; Saleil, Baptiste; Schmidt, Bill; Srinivasaraghavan, Rajalakshmi; Srivatsan, Shricharan; Thompto, Brian; Wagner, Andreas; Wu, Nelson (2021). "A matrix math facility for Power ISA(TM) processors". arXiv:2104.03142 [cs.AR].

bitsavers.org (Global: 3,844^th place; English: 1,960^th place)

Cray-1 S Series Hardware Reference Manual (PDF). Cray Research. November 1981. p. 6-12.
IBM System/370 Vector Operations (PDF) (Third ed.). IBM Corporation. August 1986. SA22-7125-2. Retrieved Sep 20, 2018.
CDC Cyber 200 Model 205 Computer System Hardware Reference Manual (PDF). Control Data Corporation. 11 November 1983.
IBM System/370 Vector Operations (PDF) (Third ed.). IBM Corporation. August 1986. SA22-7125-2. Retrieved Sep 20, 2018.

doi.org (Global: 2^nd place; English: 2^nd place)

Miyaoka, Y.; Choi, J.; Togawa, N.; Yanagisawa, M.; Ohtsuki, T. (2002). An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. Asia-Pacific Conference on Circuits and Systems. Vol. 1. pp. 171–176. doi:10.1109/APCCAS.2002.1114930. hdl:2065/10689.
Krikelis, Anargyros (1996). "A Modular Massively Parallel Processor for Volumetric Visualisation Processing". High Performance Computing for Computer Graphics and Visualisation. pp. 101–124. doi:10.1007/978-1-4471-1011-8_8. ISBN 978-3-540-76016-0.

ghostarchive.org (Global: 64^th place; English: 28^th place)

"IBM's POWER10 Processor - William Starke & Brian W. Thompto, IBM". YouTube. 25 September 2020. Archived from the original on 2021-12-11.

github.com (Global: 380^th place; English: 337^th place)

"asm-lessons/lesson_01/index.md at main · FFmpeg/asm-lessons". GitHub. Retrieved 2025-04-25.
MIAOW GPU
"Riscv-v-spec/V-spec.adoc at master · riscv/Riscv-v-spec". GitHub. 16 June 2023.
"Release Vector Extension 1.0, frozen for public review · riscvarchive/Riscv-v-spec". GitHub.
"Riscv-v-spec/V-spec.adoc at master · riscv/Riscv-v-spec". GitHub. 19 November 2022.
Videocore IV Programmer's Manual
"Riscv-v-spec/V-spec.adoc at master · riscv/Riscv-v-spec". GitHub. 19 November 2022.
RISC-V RVV ISA
RVV register gather-scatter instructions
LMUL > 1 in RVV
Videocore IV QPU
RVV fault-first loads
RVV strncpy example

globenewswire.com (Global: 2,858^th place; English: 1,554^th place)

"Andes Announces RISC-V Multicore 1024-bit Vector Processor: AX45MPV" (Press release). GlobeNewswire. 7 December 2022. Retrieved 23 December 2022.

hdl.handle.net (Global: 66^th place; English: 34^th place)

Miyaoka, Y.; Choi, J.; Togawa, N.; Yanagisawa, M.; Ohtsuki, T. (2002). An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. Asia-Pacific Conference on Circuits and Systems. Vol. 1. pp. 171–176. doi:10.1109/APCCAS.2002.1114930. hdl:2065/10689.

jbush001.github.io (Global: low place; English: low place)

Videocore IV QPU analysis by Jeff Bush

lanl.gov (Global: 5,474^th place; English: 5,230^th place)

Cray Overview

libre-soc.org (Global: low place; English: low place)

"Daxpy example".

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MIAOW Vertical Research Group

nvidia.com (Global: 2,958^th place; English: 2,263^rd place)

docs.nvidia.com

"CUDA C++ Programming Guide".

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patchwork.ozlabs.org

PATCH to libc6 to add optimised POWER9 strncpy

patents.google.com (Global: 1,154^th place; English: 606^th place)

Abandoned US patent US20110227920-0096

sakura.ne.jp (Global: low place; English: low place)

sxauroratsubasa.sakura.ne.jp

"Vector Engine Assembly Language Reference Manual" (PDF). 16 June 2023.

sigarch.org (Global: low place; English: low place)

David Patterson; Andrew Waterman (18 September 2017). "SIMD Instructions Considered Harmful". Computer Architecture Today. Unlike SIMD, it has a vector length register vl, which makes the vector instructions work at any value of n.
SIMD considered harmful
"SIMD Instructions Considered Harmful". 18 September 2017.

springer.com (Global: 182^nd place; English: 172^nd place)

link.springer.com

Krikelis, Anargyros (1996). "A Modular Massively Parallel Processor for Volumetric Visualisation Processing". High Performance Computing for Computer Graphics and Visualisation. pp. 101–124. doi:10.1007/978-1-4471-1011-8_8. ISBN 978-3-540-76016-0.

stackoverflow.com (Global: 9,249^th place; English: 6,951^st place)

sx-aurora.github.io (Global: low place; English: low place)

SX-Arora Overview

taylorandfrancis.com (Global: low place; English: low place)

"Knowledge and References". Taylor & Francis. 2015-05-03. Retrieved 2026-02-19.

vimeo.com (Global: 1,259^th place; English: 860^th place)

"Tom Forsyth - the Lifecycle of an Instruction Set". 22 August 2020.

youtube.com (Global: 13^th place; English: 14^th place)

m.youtube.com

"IBM's POWER10 Processor - William Starke & Brian W. Thompto, IBM". YouTube. 25 September 2020. Archived from the original on 2021-12-11.

Vector processor (English Wikipedia)

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