Vector processor (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Vector processor" in English language version.

refsWebsite

Global rank English rank

11github.com

383^rd place

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4arm.com

4,773^rd place

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2archive.org

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2doi.org

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2cmu.edu

1,564^th place

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2stackoverflow.com

4,643^rd place

2,973^rd place

1miaowgpu.org

low place

1globenewswire.com

2,614^th place

1,549^th place

1handle.net

102^nd place

76^th place

1sakura.ne.jp

1,806^th place

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1thebeardsage.com

low place

1ed.ac.uk

1,871^st place

1,234^th place

1jbush001.github.io

low place

1sigarch.org

low place

1lanl.gov

3,495^th place

2,913^th place

1sx-aurora.github.io

low place

1youtube.com

9^th place

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1ghostarchive.org

32^nd place

21^st place

1arxiv.org

69^th place

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1springer.com

274^th place

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1nvidia.com

2,503^rd place

1,760^th place

1patents.google.com

1,182^nd place

725^th place

1ozlabs.org

low place

1alastairreid.github.io

low place

alastairreid.github.io

ARM SVE2 paper by N. Stevens

archive.org

Parkinson, Dennis (17 June 1976). "Computers by the thousand". New Scientist. pp. 626–627. Retrieved 7 July 2024.
Patterson, David A.; Hennessy, John L. (1998). Computer Organization and Design: the Hardware/Software Interface page 751-2 (2nd ed.). Morgan Kaufmann. p. 751-2. ISBN 155860491X.

arm.com

developer.arm.com

community.arm.com

"Coding for Neon - Part 3 Matrix Multiplication". 11 September 2013.

arxiv.org

Moreira, José E.; Barton, Kit; Battle, Steven; Bergner, Peter; Bertran, Ramon; Bhat, Puneeth; Caldeira, Pedro; Edelsohn, David; Fossum, Gordon; Frey, Brad; Ivanovic, Nemanja; Kerchner, Chip; Lim, Vincent; Kapoor, Shakti; Tulio Machado Filho; Silvia Melitta Mueller; Olsson, Brett; Sadasivam, Satish; Saleil, Baptiste; Schmidt, Bill; Srinivasaraghavan, Rajalakshmi; Srivatsan, Shricharan; Thompto, Brian; Wagner, Andreas; Wu, Nelson (2021). "A matrix math facility for Power ISA(TM) processors". arXiv:2104.03142 [cs.AR].

cmu.edu

course.ece.cmu.edu

doi.org

Miyaoka, Y.; Choi, J.; Togawa, N.; Yanagisawa, M.; Ohtsuki, T. (2002). An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. Asia-Pacific Conference on Circuits and Systems. Vol. 1. pp. 171–176. doi:10.1109/APCCAS.2002.1114930. hdl:2065/10689.
Krikelis, Anargyros (1996). "A Modular Massively Parallel Processor for Volumetric Visualisation Processing". High Performance Computing for Computer Graphics and Visualisation. pp. 101–124. doi:10.1007/978-1-4471-1011-8_8. ISBN 978-3-540-76016-0.

ed.ac.uk

inf.ed.ac.uk

Vector and SIMD processors, slides 12-13

ghostarchive.org

"IBM's POWER10 Processor - William Starke & Brian W. Thompto, IBM". YouTube. Archived from the original on 2021-12-11.

github.com

MIAOW GPU
"Riscv-v-spec/V-spec.adoc at master · riscv/Riscv-v-spec". GitHub. 16 June 2023.
"Riscv-v-spec/V-spec.adoc at master · riscv/Riscv-v-spec". GitHub. 19 November 2022.
Videocore IV Programmer's Manual
"Riscv-v-spec/V-spec.adoc at master · riscv/Riscv-v-spec". GitHub. 19 November 2022.
RISC-V RVV ISA
RVV register gather-scatter instructions
LMUL > 1 in RVV
Videocore IV QPU
RVV fault-first loads
RVV strncpy example

globenewswire.com

"Andes Announces RISC-V Multicore 1024-bit Vector Processor: AX45MPV" (Press release). GlobeNewswire. 7 December 2022. Retrieved 23 December 2022.

handle.net

hdl.handle.net

Miyaoka, Y.; Choi, J.; Togawa, N.; Yanagisawa, M.; Ohtsuki, T. (2002). An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. Asia-Pacific Conference on Circuits and Systems. Vol. 1. pp. 171–176. doi:10.1109/APCCAS.2002.1114930. hdl:2065/10689.