Analysis of information sources in references of the Wikipedia article "Addressing mode" in English language version.
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79% of all instructions executed could be replaced by RISC instructions or synthesized into RISC instructions using only basic block instruction combination.
Figure 2-9: Effective Address Calculation: test "PI RQ ?"
The C54x has 17 data addressing modes, not counting register access, but the four found in MIPS account for 70% of the modes. Autoincrement and autodecrement, found in some RISC architectures, account for another 25% of the usage. This data was collected form a measurement of static instructions for the C-callable library of 54 DSP routines coded in assembly language.
3 programs measured on machine with all address modes (VAX) ... 75% displacement and immediate
79% of all instructions executed could be replaced by RISC instructions or synthesized into RISC instructions using only basic block instruction combination.
79% of all instructions executed could be replaced by RISC instructions or synthesized into RISC instructions using only basic block instruction combination.
... MIPS-X uses a single addressing mode: base register plus offset. This simple addressing mode allows the computation of the effective address to begin very early ...
The LEA (load effective address) instruction computes the effective address in memory (offset within a segment) of a source operand and places it in a general-purpose register. This instruction can interpret any of the processor's addressing modes and can perform any indexing or scaling that may be needed. It is especially useful for initializing the ESI or EDI registers before the execution of string instructions or for initializing the EBX register before an XLAT instruction.
3 programs measured on machine with all address modes (VAX) ... 75% displacement and immediate
