And-inverter graph (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "And-inverter graph" in English language version.

refsWebsite

Global rank English rank

5doi.org

2^nd place

5psu.edu

207^th place

136^th place

2harvard.edu

18^th place

17^th place

1perbjesse.com

low place

1umich.edu

459^th place

360^th place

1berkeley.edu

580^th place

462^nd place

1semanticscholar.org

11^th place

8^th place

1ntt.co.jp

low place

1ibm.com

1,131^st place

850^th place

berkeley.edu (Global: 580^th place; English: 462^nd place)

eecs.berkeley.edu

A. Mishchenko; J. S. Zhang; S. Sinha; J. R. Burch; R. Brayton; M. Chrzanowska-Jeske (May 2006). "Using simulation and satisfiability to compute flexibilities in Boolean networks" (PDF). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25 (5): 743–755. Bibcode:2006ITCAD..25..743M. CiteSeerX 10.1.1.62.8602. doi:10.1109/tcad.2005.860955. S2CID 13099806.

doi.org (Global: 2^nd place; English: 2^nd place)

Hellerman, Leo (June 1963). "A Catalog of Three-Variable Or-Invert and And-Invert Logical Circuits". IEEE Transactions on Electronic Computers. EC-12 (3): 198–223. doi:10.1109/PGEC.1963.263531.
A. Darringer; W. H. Joyner, Jr.; C. L. Berman; L. Trevillyan (Jul 1981). "Logic synthesis through local transformations". IBM Journal of Research and Development. 25 (4): 272–280. CiteSeerX 10.1.1.85.7515. doi:10.1147/rd.254.0272.
G. L. Smith; R. J. Bahnsen; H. Halliwell (Jan 1982). "Boolean comparison of hardware and flowcharts". IBM Journal of Research and Development. 26 (1): 106–116. CiteSeerX 10.1.1.85.2196. doi:10.1147/rd.261.0106.
A. Kuehlmann; V. Paruthi; F. Krohm; M. K. Ganai (2002). "Robust boolean reasoning for equivalence checking and functional property verification". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21 (12): 1377–1394. Bibcode:2002ITCAD..21.1377K. CiteSeerX 10.1.1.119.9047. doi:10.1109/tcad.2002.804386.
A. Mishchenko; J. S. Zhang; S. Sinha; J. R. Burch; R. Brayton; M. Chrzanowska-Jeske (May 2006). "Using simulation and satisfiability to compute flexibilities in Boolean networks" (PDF). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25 (5): 743–755. Bibcode:2006ITCAD..25..743M. CiteSeerX 10.1.1.62.8602. doi:10.1109/tcad.2005.860955. S2CID 13099806.

harvard.edu (Global: 18^th place; English: 17^th place)

ui.adsabs.harvard.edu

A. Kuehlmann; V. Paruthi; F. Krohm; M. K. Ganai (2002). "Robust boolean reasoning for equivalence checking and functional property verification". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21 (12): 1377–1394. Bibcode:2002ITCAD..21.1377K. CiteSeerX 10.1.1.119.9047. doi:10.1109/tcad.2002.804386.
A. Mishchenko; J. S. Zhang; S. Sinha; J. R. Burch; R. Brayton; M. Chrzanowska-Jeske (May 2006). "Using simulation and satisfiability to compute flexibilities in Boolean networks" (PDF). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25 (5): 743–755. Bibcode:2006ITCAD..25..743M. CiteSeerX 10.1.1.62.8602. doi:10.1109/tcad.2005.860955. S2CID 13099806.

ibm.com (Global: 1,131^st place; English: 850^th place)

public.dhe.ibm.com

J. Baumgartner; A. Kuehlmann (2001). "Min-area retiming on flexible circuit structures" (PDF). Proc. ICCAD'01. pp. 176–182.

ntt.co.jp (Global: low place; English: low place)

kecl.ntt.co.jp

S. Yamashita; H. Sawada; A. Nagoya (1996). "A new method to express functional permissibilities for LUT based FPGAs and its applications" (PDF). Proc. ICCAD. pp. 254–261.

perbjesse.com (Global: low place; English: low place)

Per Bjesse; Arne Borälv (2004). "DAG-aware circuit compression for formal verification" (PDF). Proc. ICCAD '04. pp. 42–49.

psu.edu (Global: 207^th place; English: 136^th place)

citeseerx.ist.psu.edu

A. Darringer; W. H. Joyner, Jr.; C. L. Berman; L. Trevillyan (Jul 1981). "Logic synthesis through local transformations". IBM Journal of Research and Development. 25 (4): 272–280. CiteSeerX 10.1.1.85.7515. doi:10.1147/rd.254.0272.
G. L. Smith; R. J. Bahnsen; H. Halliwell (Jan 1982). "Boolean comparison of hardware and flowcharts". IBM Journal of Research and Development. 26 (1): 106–116. CiteSeerX 10.1.1.85.2196. doi:10.1147/rd.261.0106.
A. Kuehlmann; V. Paruthi; F. Krohm; M. K. Ganai (2002). "Robust boolean reasoning for equivalence checking and functional property verification". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21 (12): 1377–1394. Bibcode:2002ITCAD..21.1377K. CiteSeerX 10.1.1.119.9047. doi:10.1109/tcad.2002.804386.
A. Mishchenko; J. S. Zhang; S. Sinha; J. R. Burch; R. Brayton; M. Chrzanowska-Jeske (May 2006). "Using simulation and satisfiability to compute flexibilities in Boolean networks" (PDF). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25 (5): 743–755. Bibcode:2006ITCAD..25..743M. CiteSeerX 10.1.1.62.8602. doi:10.1109/tcad.2005.860955. S2CID 13099806.
S. Sinha; R. K. Brayton (1998). "Implementation and use of SPFDs in optimizing Boolean networks". Proc. ICCAD. pp. 103–110. CiteSeerX 10.1.1.488.8889.

semanticscholar.org (Global: 11^th place; English: 8^th place)

api.semanticscholar.org

A. Mishchenko; J. S. Zhang; S. Sinha; J. R. Burch; R. Brayton; M. Chrzanowska-Jeske (May 2006). "Using simulation and satisfiability to compute flexibilities in Boolean networks" (PDF). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25 (5): 743–755. Bibcode:2006ITCAD..25..743M. CiteSeerX 10.1.1.62.8602. doi:10.1109/tcad.2005.860955. S2CID 13099806.

umich.edu (Global: 459^th place; English: 360^th place)

web.eecs.umich.edu

K.-H. Chang; I. L. Markov; V. Bertacco (2005). "Post-placement rewiring and rebuffering by exhaustive search for functional symmetries" (PDF). Proc. ICCAD '05. pp. 56–63.