Binary multiplier (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Binary multiplier" in English language version.

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books.google.com

Rafiquzzaman, M. (2005). "§2.5.1 Binary Arithmetic: Multiplication of Unsigned Binary Numbers". Fundamentals of Digital Logic and Microcomputer Design. Wiley. p. 46. ISBN 978-0-47173349-2.
Rafiquzzaman 2005, §7.3.3 Addition, Subtraction, Multiplication and Division of Signed and Unsigned Numbers p. 251
Kant, Krishna (2007). "§2.11.2 16-Bit Microprocessors". Microprocessors and Microcontrollers: Architecture, Programming and System Design 8085, 8086, 8051, 8096. PHI Learning. p. 57. ISBN 9788120331914.

doi.org

doi.org

Rather, Elizabeth D.; Colburn, Donald R.; Moore, Charles H. (1996) [1993]. "The evolution of Forth". In Bergin, Thomas J.; Gibson, Richard G. (eds.). History of programming languages---II. Association for Computing Machinery. pp. 625–670. doi:10.1145/234286.1057832. ISBN 0201895021.
Davies, A.C.; Fung, Y.T. (1977). "Interfacing a hardware multiplier to a general-purpose microprocessor". Microprocessors. 1 (7): 425–432. doi:10.1016/0308-5953(77)90004-6.
Baugh, Charles Richmond; Wooley, Bruce A. (December 1973). "A Two's Complement Parallel Array Multiplication Algorithm". IEEE Transactions on Computers. C-22 (12): 1045–1047. doi:10.1109/T-C.1973.223648. S2CID 7473784.
Hatamian, Mehdi; Cash, Glenn (1986). "A 70-MHz 8-bit×8-bit parallel pipelined multiplier in 2.5-μm CMOS". IEEE Journal of Solid-State Circuits. 21 (4): 505–513. Bibcode:1986IJSSC..21..505H. doi:10.1109/jssc.1986.1052564.
Reynders, Nele; Dehaene, Wim (2015). Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits. Analog Circuits and Signal Processing. Springer. doi:10.1007/978-3-319-16136-5. ISBN 978-3-319-16135-8. ISSN 1872-082X. LCCN 2015935431.

dx.doi.org

Davies, A.C.; Fung, Y.T. (1977). "Interfacing a hardware multiplier to a general-purpose microprocessor". Microprocessors. 1 (7): 425–432. doi:10.1016/0308-5953(77)90004-6.

edi-info.ir

dl.edi-info.ir

Rouholamini, Mahnoush; Kavehie, Omid; Mirbaha, Amir-Pasha; Jasbi, Somaye Jafarali; Navi, Keivan. "A New Design for 7:2 Compressors" (PDF).

forth.com

Rather, Elizabeth D.; Colburn, Donald R.; Moore, Charles H. (1996) [1993]. "The evolution of Forth". In Bergin, Thomas J.; Gibson, Richard G. (eds.). History of programming languages---II. Association for Computing Machinery. pp. 625–670. doi:10.1145/234286.1057832. ISBN 0201895021.

harvard.edu

ui.adsabs.harvard.edu

Hatamian, Mehdi; Cash, Glenn (1986). "A 70-MHz 8-bit×8-bit parallel pipelined multiplier in 2.5-μm CMOS". IEEE Journal of Solid-State Circuits. 21 (4): 505–513. Bibcode:1986IJSSC..21..505H. doi:10.1109/jssc.1986.1052564.

loc.gov

lccn.loc.gov

Reynders, Nele; Dehaene, Wim (2015). Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits. Analog Circuits and Signal Processing. Springer. doi:10.1007/978-3-319-16136-5. ISBN 978-3-319-16135-8. ISSN 1872-082X. LCCN 2015935431.

researchgate.net

Leong, Yuhao; Lo, HaiHiung; Drieberg, Michael; Sayuti, Abu Bakar; Sebastian, Patrick. "Performance Comparison Review of 8-3 compressor on FPGA".
Hatamian, Mehdi; Cash, Glenn (1986). "A 70-MHz 8-bit×8-bit parallel pipelined multiplier in 2.5-μm CMOS". IEEE Journal of Solid-State Circuits. 21 (4): 505–513. Bibcode:1986IJSSC..21..505H. doi:10.1109/jssc.1986.1052564.

semanticscholar.org

api.semanticscholar.org

Baugh, Charles Richmond; Wooley, Bruce A. (December 1973). "A Two's Complement Parallel Array Multiplication Algorithm". IEEE Transactions on Computers. C-22 (12): 1045–1047. doi:10.1109/T-C.1973.223648. S2CID 7473784.

uvic.ca

ece.uvic.ca

Gebali, Fayez (2003). "Baugh–Wooley Multiplier" (PDF). University of Victoria, CENG 465 Lab 2. Archived (PDF) from the original on 2018-04-14. Retrieved 2018-04-14.

uwindsor.ca

scholar.uwindsor.ca

Peng Chang. "A Reconfigurable Digital Multiplier and 4:2 Compressor Cells Design". 2008.

web.archive.org

Gebali, Fayez (2003). "Baugh–Wooley Multiplier" (PDF). University of Victoria, CENG 465 Lab 2. Archived (PDF) from the original on 2018-04-14. Retrieved 2018-04-14.

worldcat.org

search.worldcat.org

Reynders, Nele; Dehaene, Wim (2015). Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits. Analog Circuits and Signal Processing. Springer. doi:10.1007/978-3-319-16136-5. ISBN 978-3-319-16135-8. ISSN 1872-082X. LCCN 2015935431.