Boundary scan (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Boundary scan" in English language version.

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doi.org

Williams, M. J. Y.; Angel, J. B. (January 1973), "Enhancing Testability of Large Scale Integrated Circuits via Test Points and Additional Logic", IEEE Transactions on Computers, C-22 (1): 46–60, doi:10.1109/T-C.1973.223600, S2CID 5427856

electronicdesign.com

Frenzel, Louis E. (September 11, 2008). "The Embedded Plan For JTAG Boundary Scan". Electronic Design. Archived from the original on 2008-12-01. presents an overview, circa 2008.

embedded.com

Oshana, Rob (October 29, 2002). "Introduction to JTAG". Embedded Systems Design. Retrieved 2007-04-05.

espacenet.com

worldwide.espacenet.com

US 3761695, Eichelberger, Edward, "Method of Level Sensitive Testing a Functional Logic System", issued 9/25/1973
US 4293919, Dasgupta, Sumit, "Level sensitive scan design (LSSD) system", issued 10/06/1981

semanticscholar.org

api.semanticscholar.org

Williams, M. J. Y.; Angel, J. B. (January 1973), "Enhancing Testability of Large Scale Integrated Circuits via Test Points and Additional Logic", IEEE Transactions on Computers, C-22 (1): 46–60, doi:10.1109/T-C.1973.223600, S2CID 5427856

ti.com

focus.ti.com

IEEE Std 1149.1 (JTAG) Testability Primer Chapter 3 covers boundary scan with JTAG, and other chapters are also informative.

web.archive.org

Frenzel, Louis E. (September 11, 2008). "The Embedded Plan For JTAG Boundary Scan". Electronic Design. Archived from the original on 2008-12-01. presents an overview, circa 2008.