C-element (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "C-element" in English language version.

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10doi.org

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acm.org

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P. Beerel and T. H.-Y. Meng. "Automatic gate-level synthesis of speed-independent circuits", IEEE/ACM Int. Conference on Computer-Aided Design (ICCAD) 1992, pp. 581–587.
A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev, "Basic gate implementation of speed-independent circuits", ACM Design Automation Conference (DAC) 1994, pp. 56–62.

archive.org

D. E. Muller, Theory of asynchronous circuits. Report no. 66, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1955.
Technical Progress Report, Jan. 1959, University of Illinois at Urbana-Champaign.
W . J. Poppellbaum, N. E. Wiseman, "Circuit design for the new Illinois computer", Report no. 90, University of Illinois at Urbana-Champaign, 1959.
J. C. Nelson, Speed-independent counting circuits. Report no. 71, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1956.

async.org.uk

A. Mokhov, V. Khomenko, D. Sokolov and A. Yakovlev, "On dual-rail control logic for enhanced circuit robustness", IEEE Int. Conference on Application of Concurrency to System Design (ACSD) 2012, pp. 112–121.

bgu.ac.il

ee.bgu.ac.il

D. E. Muller and W. S. Bartky, "A theory of asynchronous circuits", Int. Symposium on the Switching Theory in Harvard University, pp. 204–243, 1959.
B. S. Tsirlin, "A Survey of Equivalent Problems of Realizing Circuits in the AND-NOT Basis that are Speed-Independent", Soviet Journal of Computer and Systems Sciences, vol. 24, 1986, pp. 58–69 (Б. С. Цирлин, "Обзор эквивалентных проблем реализации схем в базисе И-НЕ, не зависящих от скорости", Изв. АН СССР, Техническая кибернетика, №2, 1986, с. 159–171).
H. Zemanek, "Sequentielle asynchrone Logik", Elektronische Rechenanlagen, vol. 4, no. 6, pp. 248–253, 1962. Also available in Russian as Г. Цеманек, "Последовательная асинхронная логика", Mеждународный симпозиум ИФАК Теория конечных и вероятностных автоматов 1962, с. 232—245.
V. Varshavsky, B. Ovsievich, "Networks composed of ternary majority elements", IEEE Transactions on Electronic Computers, vol. EC-14, no. 5, pp. 730–733, 1965.

caltech.edu

async.caltech.edu

A. J. Martin, P. Prakash, "Asynchronous nano-electronics: Preliminary investigation" Archived 2016-03-04 at the Wayback Machine, IEEE Int. Symposium on Asynchronous Circuits and Systems (ASYNC) 2008, pp. 58–68.

degruyter.com

H. Zemanek, "Sequentielle asynchrone Logik", Elektronische Rechenanlagen, vol. 4, no. 6, pp. 248–253, 1962. Also available in Russian as Г. Цеманек, "Последовательная асинхронная логика", Mеждународный симпозиум ИФАК Теория конечных и вероятностных автоматов 1962, с. 232—245.

doi.org

Kimura, Izumi (1971). "Extensions of asynchronous circuits and the delay problem. Part II: Spike-free extensions and the delay problem of the second kind". Journal of Computer and System Sciences. 5 (2): 129–162. doi:10.1016/S0022-0000(71)80031-4.
Kushnerov, Alex; Bystrov, Sergey (2023). "Signal Transition Graphs for Asynchronous Data Path Circuits". Modeling and Analysis of Information Systems. 30 (2): 170–186. doi:10.18255/1818-1015-2023-2-170-186.
Gunawardena, Jeremy (1993). "A generalized event structure for the Muller unfolding of a safe net". Concur'93. Lecture Notes in Computer Science. Vol. 715. pp. 278–292. doi:10.1007/3-540-57208-2_20. ISBN 978-3-540-57208-4.
Stucki, Mishell J.; Ornstein, Severo M.; Clark, Wesley A. (1967). "Logical design of macromodules". Proceedings of the April 18-20, 1967, spring joint computer conference on - AFIPS '67 (Spring). pp. 357–364. doi:10.1145/1465482.1465538. ISBN 978-1-4503-7895-6.
Beerel, Peter A.; Burch, Jerry R.; Meng, Teresa H. (1998). "Checking Combinational Equivalence of Speed-Independent Circuits". Formal Methods in System Design. 13 (1): 37–85. doi:10.1023/A:1008666605437.
Varshavsky, V.I. (1998). "β-driven threshold elements". Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222). pp. 52–58. doi:10.1109/GLSV.1998.665199. ISBN 0-8186-8409-7.
Pucknell, D.A. (1993). "Event-driven logic (EDL) approach to digital systems representation and related design processes". IEE Proceedings E - Computers and Digital Techniques. 140 (2): 119–126. doi:10.1049/ip-e.1993.0018.
Glosekotter, P.; Pacha, C.; Goser, K.F.; Prost, W.; Kim, S.; Van Husen, H.; Reimann, T.; Tegude, F.J. (2002). "Asynchronous circuit design based on the RTBT monostable-bistable logic transition element (MOBILE)". Proceedings. 15th Symposium on Integrated Circuits and Systems Design. pp. 365–370. doi:10.1109/SBCCI.2002.1137684. ISBN 0-7695-1807-9.
Brzozowski, J.A.; Raahemifar, K. (1995). "Testing C-elements is not elementary". Proceedings Second Working Conference on Asynchronous Design Methodologies. pp. 150–159. doi:10.1109/WCADM.1995.514652. ISBN 0-8186-7098-3.
Yakovlev, A. V.; Koelmans, A. M.; Semenov, A.; Kinniment, D. J. (December 1996). "Modelling, analysis and synthesis of asynchronous control circuits using Petri nets". Integration. 21 (3): 143–170. doi:10.1016/S0167-9260(96)00010-7.

espacenet.com

worldwide.espacenet.com

V. I. Varshavsky, N. M. Kravchenko, V. B. Marakhovsky, B. S. Tsirlin, "H flip-flop", USSR author's certificate SU1562964, Jul. 5, 1990.
Y. A. Stepchenkov, Y. G. Dyachenko, A. N. Denisov, Y. P. Fomin, "H flip-flop", Patent RU2371842, Oct. 27, 2009.
D. Hampel, K. Prost, and N. Scheingberg, "Threshold logic using complementary MOS device", Patent US3900742, Aug. 19, 1975.
W. Fleischhammer, "Improvements in or relating to asynchronous bistable trigger circuits", UK patent specification GB1199698, Jul. 22, 1970.
V. I. Varshavsky, A. Y. Kondratyev, N. M. Kravchenko, and B. S. Tsirlin, "H flip-flop", USSR Author's certificate SU1411934 Jul. 23, 1988.
V. I. Varshavsky, N. M. Kravchenko, V. B. Marakhovsky and B. S. Tsirlin, "H flip-flop", USSR Author's certificate SU1443137, Dec. 7, 1988.
S. M. Fairbanks, "Two-stage Muller C-element", United States Patent US6281707, Aug. 28, 2001.

freepatentsonline.com

V. I. Varshavsky, "Threshold element and method of designing the same," Patent US6338157, Jan. 8, 2002.

ieee.org

ieeexplore.ieee.org

Varshavsky, V.I. (1998). "β-driven threshold elements". Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222). pp. 52–58. doi:10.1109/GLSV.1998.665199. ISBN 0-8186-8409-7.
T.-Y. Wuu and S. B. K. Vrudhula, "A design of a fast and area efficient multi-input Muller C-element", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, no. 2, pp. 215–219, 1993.
H. K. O. Berge, A. Hasanbegovic, S. Aunet, "Muller C-elements based on minority-3 functions for ultra low voltage supplies", IEEE Int. Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) 2011, pp. 195–200.
C.-H. Lin, K. Yang, A. F. Gonzalez, J. R. East, P. Mazumder, G. I. Haddad, "InP-based high speed digital logic gates using an RTD/HBT heterostructure", Int. Conference on Indium Phosphide and Related Materials (IPRM) 1999, pp. 419–422.
Glosekotter, P.; Pacha, C.; Goser, K.F.; Prost, W.; Kim, S.; Van Husen, H.; Reimann, T.; Tegude, F.J. (2002). "Asynchronous circuit design based on the RTBT monostable-bistable logic transition element (MOBILE)". Proceedings. 15th Symposium on Integrated Circuits and Systems Design. pp. 365–370. doi:10.1109/SBCCI.2002.1137684. ISBN 0-7695-1807-9.
M. Kuwako, T. Nanya, "Timing-reliability evaluation of asynchronous circuits based on different delay models", IEEE Int. Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC) 1994, pp. 22–31.
Brzozowski, J.A.; Raahemifar, K. (1995). "Testing C-elements is not elementary". Proceedings Second Working Conference on Asynchronous Design Methodologies. pp. 150–159. doi:10.1109/WCADM.1995.514652. ISBN 0-8186-7098-3.
N. A. Starodoubtsev, S. A. Bystrov, "Monotonic behavior refinement for synthesis of two-input-gate asynchronous circuits", IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS) 2004, vol. I, pp. I-521–524.
J. P. Murphy, "Design of latch-based C-element", Electronics Letters, vol. 48, no. 19, 2012, pp. 1190–1191.
V. I. Varshavsky, "Logic design and quantum challenge", Int. Workshop on Physics and Computer Modeling of Devices Based on Low-Dimensional Structures 1995, pp. 134–146.

jstor.org

Kimura, Izumi (1969). "A comparison between two mathematical models of asynchronous circuits". Science Reports of the Tokyo Kyoiku Daigaku, Section A. 10 (232/248): 109–123. JSTOR 43698723.

mit.edu

publications.csail.mit.edu

N. P. Singh, A design methodology for self-timed systems. MSc thesis, MIT, 1981, 98 p.

nii.ac.jp

glim-re.repo.nii.ac.jp

H. Sato, Completeness on Multiple-Valued Logical Functions Realized by Asynchronous Sequential Circuits. PhD thesis, Gakushuin University, 1996.

pdx.edu

pdxscholar.library.pdx.edu

H. Park, A. He, M. Roncken and X. Song, "Semi-modular delay model revisited in context of relative timing", IET Electronics Letters, vol. 51, no. 4, pp. 332–334, 2015.

proquest.com

J. M. Johnson, Theory and Application of Self-Timed Integrated Systems Using Ternary Logic Elements. PhD thesis. University of California, Santa Barbara. 1989.

psu.edu

citeseerx.ist.psu.edu

C. H. van Berkel, "Beware the isochronic fork", Report UR 003/91, Philips Research Laboratories, 1991.
A. Yakovlev, M. Kishinevsky, A. Kondratyev, L. Lavagno, M. Pietkiewicz-Koutny, "On the models for asynchronous circuit behaviour with OR causality", Formal Methods in System Design, vol. 9, no. 3, pp. 189—233. 1996.
V. Beiu, J. M. Quintana, M. J. Avedillo, "VLSI implementations of threshold logic – A comprehensive survey", IEEE Transactions on Neural Networks, vol. 14, no. 5, pp. 1217–1243, 2003.

citeseer.ist.psu.edu

A. Bystrov, A. Yakovlev, Asynchronous circuit synthesis by direct mapping: Interfacing to environment. Technical Report, CS Department, University of Newcastle upon Tyne, October 2001.

pucrs.br

inf.pucrs.br

J. Cortadella, M. Kishinevsky, Tutorial: Synthesis of control circuits from STG specifications. Summer school, Lyngby, 1997.

researchgate.net

V. Varshavskiy, M. Kishinevskiy, V. Marakhovskiy, L. Rozenblyum, "Functional completeness in the class of semimodular circuits," Soviet Journal of Computer and Systems Sciences, vol. 23, no. 6, pp. 70-80, 1985.
S. Safiruddin, S. D. Cotofana, "Building blocks for delay-insensitive circuits using single electron tunneling devices", IEEE Conference on Nanotechnology 2007, pp. 704–708.

sainsburysebooks.co.uk

samples.sainsburysebooks.co.uk

D. Doman, Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon Archived 2015-10-08 at the Wayback Machine. Wiley, 2012, 327 p.

sciencedirect.com

Kimura, Izumi (1971). "Extensions of asynchronous circuits and the delay problem. Part II: Spike-free extensions and the delay problem of the second kind". Journal of Computer and System Sciences. 5 (2): 129–162. doi:10.1016/S0022-0000(71)80031-4.
Yakovlev, A. V.; Koelmans, A. M.; Semenov, A.; Kinniment, D. J. (December 1996). "Modelling, analysis and synthesis of asynchronous control circuits using Petri nets". Integration. 21 (3): 143–170. doi:10.1016/S0167-9260(96)00010-7.

seul.org

f-cpu.seul.org

I. E. Sutherland, "Micropipelines", Communications of the ACM, vol. 32, no. 6, pp. 720–738, 1989.

spbstu.ru

elib.spbstu.ru

V. B. Marakhovsky, Logic design of asynchronous circuits. Slides on the course. CS&SE Department, SPbPU.

springer.com

link.springer.com

Beerel, Peter A.; Burch, Jerry R.; Meng, Teresa H. (1998). "Checking Combinational Equivalence of Speed-Independent Circuits". Formal Methods in System Design. 13 (1): 37–85. doi:10.1023/A:1008666605437.
P. A. Beerel, J. R. Burch, T. H. Meng, "Checking combinational equivalence of speed-independent circuits", Formal Methods in System Design, vol. 13, no. 1, 1998, pp. 37–85.

storage.googleapis.com

patentimages.storage.googleapis.com

B. S. Tsirlin, "H flip-flop", USSR author's certificate SU1096759, Jun. 7, 1984.
B. S. Tsirlin, "Multiple input H flip-flop", USSR author's certificate SU1162019, Jun. 15, 1985.
V. I. Varshavsky, O. V. Maevsky, Yu. V. Mamrukov, B. S. Tsirlin, "H flip-flop", USSR author's certificate SU1081801, Mar. 23, 1984
G. S. Brailovsky, L. Ya. Rozenblyum, B. S. Tsirlin, "H-flip-flop", USSR author's certificate SU1432733, Oct. 23, 1988.
B. S. Tsirlin, "H-flip-flop", USSR author's certificate SU1324106, Jul. 15, 1987.

technion.ac.il

webee.technion.ac.il

K. S. Stevens, R. Ginosar and S. Rotem, "Relative timing [asynchronous design]", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 1, pp. 129–140, 2003.
A. Morgenshtein, M. Moreinis, R. Ginosar, "Asynchronous gate-diffusion-input (GDI) circuits", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 8, pp. 847–856, 2004.

uni-stuttgart.de

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uwaterloo.ca

cs.uwaterloo.ca

J. C. Ebergen, J. Segers, I. Benko, "Parallel Program and Asynchronous Circuit Design", Workshops in Computing, pp. 50–103, 1995.

web.archive.org

D. Doman, Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon Archived 2015-10-08 at the Wayback Machine. Wiley, 2012, 327 p.
M. Courvoisier and P. Azema, "Asynchronous sequential machines with request/acknowledge operating mode," IEE Electronics Letters, Vol. 10, no. 1, pp.8-10, 1974.
A. J. Martin, P. Prakash, "Asynchronous nano-electronics: Preliminary investigation" Archived 2016-03-04 at the Wayback Machine, IEEE Int. Symposium on Asynchronous Circuits and Systems (ASYNC) 2008, pp. 58–68.

yandex.ru

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