Rogenmoser, R.; Kaeslin, H. (July 1997). "The impact of transistor sizing on power efficiency in submicron CMOS circuits". IEEE Journal of Solid-State Circuits. 32 (7): 1142–1145. Bibcode:1997IJSSC..32.1142R. doi:10.1109/4.597307. S2CID15703793.
Iranmanesh, S.; Rodriguez-Villegas, E. (June 2016). "CMOS implementation of a low power absolute value comparator circuit". 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS). IEEE Newcas. pp. 1–4. doi:10.1109/NEWCAS.2016.7604807. ISBN978-1-4673-8900-6. S2CID10810576.
Rogenmoser, R.; Kaeslin, H. (July 1997). "The impact of transistor sizing on power efficiency in submicron CMOS circuits". IEEE Journal of Solid-State Circuits. 32 (7): 1142–1145. Bibcode:1997IJSSC..32.1142R. doi:10.1109/4.597307. S2CID15703793.
Rogenmoser, R.; Kaeslin, H. (July 1997). "The impact of transistor sizing on power efficiency in submicron CMOS circuits". IEEE Journal of Solid-State Circuits. 32 (7): 1142–1145. Bibcode:1997IJSSC..32.1142R. doi:10.1109/4.597307. S2CID15703793.
Iranmanesh, S.; Rodriguez-Villegas, E. (June 2016). "CMOS implementation of a low power absolute value comparator circuit". 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS). IEEE Newcas. pp. 1–4. doi:10.1109/NEWCAS.2016.7604807. ISBN978-1-4673-8900-6. S2CID10810576.