Control register (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Control register" in English language version.

Last modified: 07:10:15, 3 August 2026 (UTC)

Ref.Un. Ref.Website

Global rank English rank

97web.archive.org

1^st place

85intel.com

1,727^th place

1,234^th place

65bitsavers.org

3,844^th place

1,960^th place

22ibm.com

1,369^th place

968^th place

21amd.com

2,753^rd place

2,229^th place

11uu.se

3,445^th place

3,148^th place

11kib.kiev.ua

low place

11ncsi.com

low place

11lwn.net

4,372^nd place

3,269^th place

amd.com (Global: 2,753^rd place; English: 2,229^th place)

developer.amd.com

"AMD64 Architecture Programmer's Manual Volume 2: System Programming" (PDF). AMD. September 2012. pp. 127 & 130. Archived (PDF) from the original on 2014-02-22. Retrieved 2017-08-04.

bitsavers.org (Global: 3,844^th place; English: 1,960^th place)

M67prelim, pp. 25-26, Control Registers.
M67, p. 16, Table 4. Control Registers.
S/370, pp. 4-8-4-11 , Control Registers.
M67, pp. 31-35, Control Register Bit Assignments for Sensing.
Intel486 Microprocessor Family Programmer's Reference Manual (PDF). Intel. 1992. p. 4-7.

ibm.com (Global: 1,369^th place; English: 968^th place)

publibz.boulder.ibm.com

S/390-ESA, pp. 4-6-4-10, Control Registers.

vm.ibm.com

z/Architecture, pp. 4-9–4-12, Control Registers.

intel.com (Global: 1,727^th place; English: 1,234^th place)

software.intel.com

"5-Level Paging and 5-Level EPT" (PDF). Intel. May 2017. p. 16. Archived (PDF) from the original on 2018-12-05. Retrieved 2018-01-23.
"Intel 64 and IA-32 Architectures Software Developer's Manual" (PDF). Intel® Corporation. 2021-06-28. Retrieved 2021-09-21.
"Chapter 13, Managing State Using The Xsave Feature Set" (PDF). Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture. Intel Corporation (2019). Archived (PDF) from the original on 23 March 2019. Retrieved 23 March 2019.

intel.com

Intel Corporation (2016). "4.10.1 Process-Context Identifiers (PCIDs)". Intel 64 and IA-32 Architectures Software Developer's Manual (PDF). Vol. 3A: System Programming Guide, Part 1. Archived (PDF) from the original on 2018-02-16. Retrieved 2018-01-05.
Software Guard Extensions Programming Reference (PDF). Intel. October 2014. 329298-002. Makes no mention of CR4.SEE.

kib.kiev.ua (Global: low place; English: low place)

Software Guard Extensions Programming Reference (PDF). Intel. September 2013. 329298-001. Chapters 1.7 and 6.5.2 describe CR4.SEE.

lwn.net (Global: 4,372^nd place; English: 3,269^th place)

Anvin, H. Peter (2012-09-21). "x86: Supervisor Mode Access Prevention". LWN.net. Archived from the original on 2017-08-05. Retrieved 2017-08-04.

ncsi.com (Global: low place; English: low place)

Fischer, Stephen (2011-09-21). "Supervisor Mode Execution Protection" (PDF). NSA Trusted Computing Conference 2011. National Conference Services, Inc. Archived from the original (PDF) on 2016-08-03. Retrieved 2017-08-04.

uu.se (Global: 3,445^th place; English: 3,148^th place)

it.uu.se

"lab4.pdf" (PDF). Uppsala University. March 17, 2024. Archived (PDF) from the original on January 17, 2021. Retrieved March 16, 2024.

web.archive.org (Global: 1^st place; English: 1^st place)

"lab4.pdf" (PDF). Uppsala University. March 17, 2024. Archived (PDF) from the original on January 17, 2021. Retrieved March 16, 2024.
Intel Corporation (2016). "4.10.1 Process-Context Identifiers (PCIDs)". Intel 64 and IA-32 Architectures Software Developer's Manual (PDF). Vol. 3A: System Programming Guide, Part 1. Archived (PDF) from the original on 2018-02-16. Retrieved 2018-01-05.
"AMD64 Architecture Programmer's Manual Volume 2: System Programming" (PDF). AMD. September 2012. pp. 127 & 130. Archived (PDF) from the original on 2014-02-22. Retrieved 2017-08-04.
"5-Level Paging and 5-Level EPT" (PDF). Intel. May 2017. p. 16. Archived (PDF) from the original on 2018-12-05. Retrieved 2018-01-23.
Fischer, Stephen (2011-09-21). "Supervisor Mode Execution Protection" (PDF). NSA Trusted Computing Conference 2011. National Conference Services, Inc. Archived from the original (PDF) on 2016-08-03. Retrieved 2017-08-04.
Anvin, H. Peter (2012-09-21). "x86: Supervisor Mode Access Prevention". LWN.net. Archived from the original on 2017-08-05. Retrieved 2017-08-04.
"Chapter 13, Managing State Using The Xsave Feature Set" (PDF). Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture. Intel Corporation (2019). Archived (PDF) from the original on 23 March 2019. Retrieved 23 March 2019.

Control register (English Wikipedia)

amd.com (Global: 2,753rd place; English: 2,229th place)