Depletion-load NMOS logic (English Wikipedia)

"Motorola Redesigns 6800" (PDF). Microcomputer Digest. 3 (2). Santa Clara, CA: Microcomputer Associates: 4. August 1976. "Motorola is redesigning the M6800 microprocessor family by adding depletion loads to increase speed and reduce the 6800 CPU size to 160 mils."

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"1960 - Metal Oxide Semiconductor (MOS) Transistor Demonstrated". The Silicon Engine. Computer History Museum.

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See for instance: http://www.intel4004.com/sgate.htm or http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf Archived 2017-01-10 at the Wayback Machine

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Sah, Chih-Tang; Leistiko, Otto; Grove, A. S. (May 1965). "Electron and hole mobilities in inversion layers on thermally oxidized silicon surfaces". IEEE Transactions on Electron Devices. 12 (5): 248–254. Bibcode:1965ITED...12..248L. doi:10.1109/T-ED.1965.15489.
Critchlow, D. L. (2007). "Recollections on MOSFET Scaling". IEEE Solid-State Circuits Society Newsletter. 12 (1): 19–22. doi:10.1109/N-SSC.2007.4785536.
Atwood, G.E.; Dun, H.; Langston, J.; Hazani, E.; So, E.Y.; Sachdev, S.; Fuchs, K. (October 1982). "HMOS III technology". IEEE Journal of Solid-State Circuits. 17 (5): 810–5. Bibcode:1982IJSSC..17..810A. doi:10.1109/JSSC.1982.1051823. S2CID 1215664.

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Sah, Chih-Tang; Leistiko, Otto; Grove, A. S. (May 1965). "Electron and hole mobilities in inversion layers on thermally oxidized silicon surfaces". IEEE Transactions on Electron Devices. 12 (5): 248–254. Bibcode:1965ITED...12..248L. doi:10.1109/T-ED.1965.15489.
Atwood, G.E.; Dun, H.; Langston, J.; Hazani, E.; So, E.Y.; Sachdev, S.; Fuchs, K. (October 1982). "HMOS III technology". IEEE Journal of Solid-State Circuits. 17 (5): 810–5. Bibcode:1982IJSSC..17..810A. doi:10.1109/JSSC.1982.1051823. S2CID 1215664.

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"Prologues". Hp9825.com. Retrieved 2022-03-15.

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Volk, A.M.; Stoll, P.A.; Metrovich, P. (2001). "Recollections of Early Chip Development at Intel" (PDF). Intel Technology Journal. 5 (Q1).

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See for instance: http://www.intel4004.com/sgate.htm or http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf Archived 2017-01-10 at the Wayback Machine

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Sah, Chih-Tang; Leistiko, Otto; Grove, A. S. (May 1965). "Electron and hole mobilities in inversion layers on thermally oxidized silicon surfaces". IEEE Transactions on Electron Devices. 12 (5): 248–254. Bibcode:1965ITED...12..248L. doi:10.1109/T-ED.1965.15489.

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Atwood, G.E.; Dun, H.; Langston, J.; Hazani, E.; So, E.Y.; Sachdev, S.; Fuchs, K. (October 1982). "HMOS III technology". IEEE Journal of Solid-State Circuits. 17 (5): 810–5. Bibcode:1982IJSSC..17..810A. doi:10.1109/JSSC.1982.1051823. S2CID 1215664.

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Pseudo nMOS means that an enhancement-mode p-channel transistor with grounded gate is used in place of the depletion-mode n-channel transistor. See http://eia.udg.es/~forest/VLSI/lect.10.pdf

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See for instance: http://www.intel4004.com/sgate.htm or http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf Archived 2017-01-10 at the Wayback Machine

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See for instance: Scanlon, Leo J.; Moody, C.W. (1981). The 68000 Principles and programming. H.W. Sams. ISBN 978-0-672-21853-8. OCLC 7802969.

Depletion-load NMOS logic (English Wikipedia)

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