EEPROM (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "EEPROM" in English language version.

refsWebsite

Global rank English rank

13patents.google.com

1,182^nd place

725^th place

12web.archive.org

1^st place

11doi.org

2^nd place

8harvard.edu

18^th place

17^th place

8worldcat.org

5^th place

7semanticscholar.org

11^th place

8^th place

3books.google.com

3^rd place

2cam.ac.uk

670^th place

480^th place

1micron.com

low place

1techtarget.com

2,435^th place

1,699^th place

1jst.go.jp

1,903^rd place

2,346^th place

1tmdn.org

low place

1inpit.go.jp

8,800^th place

low place

1uspto.gov

1,459^th place

991^st place

1computerhistory.org

2,213^th place

1,495^th place

1wikiwix.com

194^th place

643^rd place

1datasheets360.com

low place

1antiquetech.com

low place

1eetimes.com

3,722^nd place

2,509^th place

1stanford.edu

179^th place

183^rd place

1usenix.org

5,990^th place

3,752^nd place

1slideshare.net

2,161^st place

2,535^th place

1ti.com

4,228^th place

2,818^th place

1rit.edu

8,676^th place

6,229^th place

1psu.edu

207^th place

136^th place

1rohm.com

low place

antiquetech.com

"Seeq Technology » AntiqueTech". Archived from the original on 2014-10-02.

books.google.com

Moskowitz, Sanford L. (2016). "reliability%20problems"+EPROM+1970s&pg=PA187 Advanced Materials Innovation: Managing Global Technology in the 21st century. John Wiley & Sons. ISBN 9781118986097.
Dummer, G. W. A. (2013). Electronic Inventions and Discoveries: Electronics from Its Earliest Beginnings to the Present Day. Elsevier. ISBN 9781483145211.
Ciarcia, Steve (1981). Ciarcia's Circuit Cellar. Circuit Cellar. ISBN 978-0-07-010963-6.

cam.ac.uk

cl.cam.ac.uk

Skorobogatov, Sergei (2017). "How Microprobing Can Attack Encrypted Memory" (PDF). 2017 Euromicro Conference on Digital System Design (DSD). 2017 Euromicro Conference on Digital System Design (DSD). Vienna. pp. 244–251. doi:10.1109/DSD.2017.69. ISBN 978-1-5386-2146-2.
"Breaking copy protection in microcontrollers". www.cl.cam.ac.uk. Archived from the original on 2017-10-22.

computerhistory.org

archive.computerhistory.org

"1027459330501acc.pdf" (PDF). Archived (PDF) from the original on 2015-02-07. Retrieved 2015-02-05.

datasheets360.com

2816A-2 PDF Datasheet - Intel Corporation - Datasheets360.com. Intel. October 1983.

doi.org

Tarui, Y.; Hayashi, Y.; Nagai, K. (1972). "Electrically reprogrammable nonvolatile semiconductor memory". IEEE Journal of Solid-State Circuits. 7 (5): 369–375. Bibcode:1972IJSSC...7..369T. doi:10.1109/JSSC.1972.1052895. ISSN 0018-9200.
Iizuka, H.; Masuoka, F.; Sato, Tai; Ishikawa, M. (1976). "Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure". IEEE Transactions on Electron Devices. 23 (4): 379–387. Bibcode:1976ITED...23..379I. doi:10.1109/T-ED.1976.18415. ISSN 0018-9383. S2CID 30491074.
Rossler, B. (1977). "Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell". IEEE Transactions on Electron Devices. 24 (5): 606–610. Bibcode:1977ITED...24..606R. doi:10.1109/T-ED.1977.18788. ISSN 0018-9383. S2CID 33203267.
Tarui, Yasuo; Nagai, Kiyoko; Hayashi, Yutaka (1974-07-19). "Nonvolatile Semiconductor Memory" (PDF). Oyo Buturi. 43 (10): 990–1002. doi:10.11470/oubutsu1932.43.990. ISSN 2188-2290. Archived (PDF) from the original on 2018-03-12.
Verwey, J. F.; Kramer, R. P. (1974). "Atmos—An electrically reprogrammable read-only memory device". IEEE Transactions on Electron Devices. 21 (10): 631–636. Bibcode:1974ITED...21..631V. doi:10.1109/T-ED.1974.17981. ISSN 0018-9383.
Gosney, W. M. (1977). "DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology". IEEE Transactions on Electron Devices. 24 (5): 594–599. Bibcode:1977ITED...24..594G. doi:10.1109/T-ED.1977.18786. ISSN 0018-9383. S2CID 45636024.
Chen, P. C. Y. (May 1977). "Threshold-alterable Si-gate MOS devices". IEEE Transactions on Electron Devices. 24 (5): 584–586. Bibcode:1977ITED...24..584C. doi:10.1109/T-ED.1977.18783. ISSN 0018-9383. S2CID 25586393.
Rossler, B. (May 1977). "Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell". IEEE Transactions on Electron Devices. 24 (5): 606–610. Bibcode:1977ITED...24..606R. doi:10.1109/T-ED.1977.18788. ISSN 0018-9383. S2CID 33203267.
Johnson, W.; Perlegos, G.; Renninger, A.; Kuhn, G.; Ranganath, T. (1980). "A 16Kb electrically erasable nonvolatile memory". 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. Vol. XXIII. pp. 152–153. doi:10.1109/ISSCC.1980.1156030. S2CID 44313709.
Euzent, B.; Boruta, N.; Lee, J.; Jenq, C. (1981). "Reliability Aspects of a Floating Gate E2 PROM". 19th International Reliability Physics Symposium. pp. 11–16. doi:10.1109/IRPS.1981.362965. S2CID 41116025. The Intel 2816 uses the FLOTOX structure, which has been discussed in detail in the literaturel. Basically, it uses an oxide of less than 200A thick between the floating polysilicon gate and the N+ region as shown in Figure 1.
Skorobogatov, Sergei (2017). "How Microprobing Can Attack Encrypted Memory" (PDF). 2017 Euromicro Conference on Digital System Design (DSD). 2017 Euromicro Conference on Digital System Design (DSD). Vienna. pp. 244–251. doi:10.1109/DSD.2017.69. ISBN 978-1-5386-2146-2.

eetimes.com

Rostky, George (July 2, 2002). "Remembering the PROM knights of Intel". EE Times. Archived from the original on September 29, 2007. Retrieved 2007-02-08.

harvard.edu

ui.adsabs.harvard.edu

Tarui, Y.; Hayashi, Y.; Nagai, K. (1972). "Electrically reprogrammable nonvolatile semiconductor memory". IEEE Journal of Solid-State Circuits. 7 (5): 369–375. Bibcode:1972IJSSC...7..369T. doi:10.1109/JSSC.1972.1052895. ISSN 0018-9200.
Iizuka, H.; Masuoka, F.; Sato, Tai; Ishikawa, M. (1976). "Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure". IEEE Transactions on Electron Devices. 23 (4): 379–387. Bibcode:1976ITED...23..379I. doi:10.1109/T-ED.1976.18415. ISSN 0018-9383. S2CID 30491074.
Rossler, B. (1977). "Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell". IEEE Transactions on Electron Devices. 24 (5): 606–610. Bibcode:1977ITED...24..606R. doi:10.1109/T-ED.1977.18788. ISSN 0018-9383. S2CID 33203267.
Verwey, J. F.; Kramer, R. P. (1974). "Atmos—An electrically reprogrammable read-only memory device". IEEE Transactions on Electron Devices. 21 (10): 631–636. Bibcode:1974ITED...21..631V. doi:10.1109/T-ED.1974.17981. ISSN 0018-9383.
B., Roessler; R. G., Mueller (1975). "Erasable and electrically reprogrammable read-only memory using the N-channel SIMOS one-transistor cell". Siemens Forschungs und Entwicklungsberichte. 4 (6): 345–351. Bibcode:1975SiFoE...4..345R.
Gosney, W. M. (1977). "DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology". IEEE Transactions on Electron Devices. 24 (5): 594–599. Bibcode:1977ITED...24..594G. doi:10.1109/T-ED.1977.18786. ISSN 0018-9383. S2CID 45636024.
Chen, P. C. Y. (May 1977). "Threshold-alterable Si-gate MOS devices". IEEE Transactions on Electron Devices. 24 (5): 584–586. Bibcode:1977ITED...24..584C. doi:10.1109/T-ED.1977.18783. ISSN 0018-9383. S2CID 25586393.
Rossler, B. (May 1977). "Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell". IEEE Transactions on Electron Devices. 24 (5): 606–610. Bibcode:1977ITED...24..606R. doi:10.1109/T-ED.1977.18788. ISSN 0018-9383. S2CID 33203267.

inpit.go.jp

j-platpat.inpit.go.jp

"Reg. No.1342184 – LIVE – REGISTRATION – Issued and Active".

jst.go.jp

jstage.jst.go.jp

Tarui, Yasuo; Nagai, Kiyoko; Hayashi, Yutaka (1974-07-19). "Nonvolatile Semiconductor Memory" (PDF). Oyo Buturi. 43 (10): 990–1002. doi:10.11470/oubutsu1932.43.990. ISSN 2188-2290. Archived (PDF) from the original on 2018-03-12.

micron.com

"TN-04-42: Memory Module Serial Presence-Detect" (PDF). Micron Technology. 2002. Archived from the original (PDF) on 2022-07-26. Retrieved 2020-10-11.

patents.google.com

US3865652A, Agusta, Benjamin; Chang, Joseph J. & Joshi, Madhukar L., "Method of forming self-aligned field effect transistor and charge-coupled device", issued 1975-02-11
Masuoka, Fujio (31 August 1972). "Avalanche injection type mos memory". {{cite journal}}: Cite journal requires |journal= (help)
US3797000A, Agusta, B. & Chang, J., "Non-volatile semiconductor storage device utilizing avalanche injection and extraction of stored information", issued 1974-03-12
US4016588A, Ohya, Shuichi & Kikuchi, Masanori, "Non-volatile semiconductor memory device", issued 1977-04-05
Rai, Yasuki; Sasami, Terutoshi; Hasegawa, Yuzuru; Okazoe, Masaru (1973-05-18). "Electrically reprogrammable nonvolatile floating gate semi-conductor memory device and method of operation". Archived from the original on 2018-05-03. {{cite journal}}: Cite journal requires |journal= (help)
Frohman, Bentchkowsky D (19 October 1973). "Electrically alterable floating gate device and method for altering same". {{cite journal}}: Cite journal requires |journal= (help)
Chou, Sunlin (26 February 1973). "Erasable floating gate device". {{cite journal}}: Cite journal requires |journal= (help)
Ohya, Shuichi; Kikuchi, Masanori (1974-12-27). "Non-volatile semiconductor memory device". {{cite journal}}: Cite journal requires |journal= (help)
Jack, S; Huang, T. (8 September 1975). "Semiconductor memory cell". {{cite journal}}: Cite journal requires |journal= (help)
GB1517925A, "Storage field effect transistors", issued 1978-07-19
Simko, Richard T. (17 March 1977). "Electrically programmable and electrically erasable MOS memory cell".
Frohman-Bentchkowsky, Dov; Mar, Jerry; Perlegos, George; Johnson, William S. (15 December 1978). "Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same".
Bergemont, Albert; Chi, Min-Hwa (1997-05-05). "US Patent 5856222: Method of fabricating a high density EEPROM cell". patents.google.com. National Semiconductor Corp.

psu.edu

citeseerx.ist.psu.edu

Groeseneken, G.; Maes, H. E.; VanHoudt, J.; Witters, J. S. Basics of Nonvolatile Semiconductor Memory Devices. CiteSeerX 10.1.1.111.9431.

rit.edu

people.rit.edu

Fuller, Dr. Lynn (2012-02-22). CMOS Process Variations EEPROM Fabrication Technology. Microelectronic Engineering, Rochester Institute of Technology.^{[permanent dead link‍]}

rohm.com

"Frequently Asked Questions -ROHM Semiconductor". Archived from the original on 2011-02-19.

semanticscholar.org

api.semanticscholar.org

Iizuka, H.; Masuoka, F.; Sato, Tai; Ishikawa, M. (1976). "Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure". IEEE Transactions on Electron Devices. 23 (4): 379–387. Bibcode:1976ITED...23..379I. doi:10.1109/T-ED.1976.18415. ISSN 0018-9383. S2CID 30491074.
Rossler, B. (1977). "Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell". IEEE Transactions on Electron Devices. 24 (5): 606–610. Bibcode:1977ITED...24..606R. doi:10.1109/T-ED.1977.18788. ISSN 0018-9383. S2CID 33203267.
Gosney, W. M. (1977). "DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology". IEEE Transactions on Electron Devices. 24 (5): 594–599. Bibcode:1977ITED...24..594G. doi:10.1109/T-ED.1977.18786. ISSN 0018-9383. S2CID 45636024.
Chen, P. C. Y. (May 1977). "Threshold-alterable Si-gate MOS devices". IEEE Transactions on Electron Devices. 24 (5): 584–586. Bibcode:1977ITED...24..584C. doi:10.1109/T-ED.1977.18783. ISSN 0018-9383. S2CID 25586393.
Rossler, B. (May 1977). "Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell". IEEE Transactions on Electron Devices. 24 (5): 606–610. Bibcode:1977ITED...24..606R. doi:10.1109/T-ED.1977.18788. ISSN 0018-9383. S2CID 33203267.
Johnson, W.; Perlegos, G.; Renninger, A.; Kuhn, G.; Ranganath, T. (1980). "A 16Kb electrically erasable nonvolatile memory". 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. Vol. XXIII. pp. 152–153. doi:10.1109/ISSCC.1980.1156030. S2CID 44313709.
Euzent, B.; Boruta, N.; Lee, J.; Jenq, C. (1981). "Reliability Aspects of a Floating Gate E2 PROM". 19th International Reliability Physics Symposium. pp. 11–16. doi:10.1109/IRPS.1981.362965. S2CID 41116025. The Intel 2816 uses the FLOTOX structure, which has been discussed in detail in the literaturel. Basically, it uses an oxide of less than 200A thick between the floating polysilicon gate and the N+ region as shown in Figure 1.

slideshare.net

Janwadkar, Sudhanshu (2017-10-24). "Fabrication of Floating Gate MOS (FLOTOX)". www.slideshare.net.

stanford.edu

cva.stanford.edu

Atmel AT28C16 datasheet (PDF) (0540B ed.). October 1998. Archived (PDF) from the original on 2017-08-29.

techtarget.com

whatis.techtarget.com

"serial presence detect (SPD)". TechTarget. July 2015.

ti.com

Koga, R.; Tran, V.; George, J.; Crawford, K.; Crain, S.; Zakrzewski, M.; Yu, P. "SEE Sensitivities of Selected Advanced Flash and First-In-First-Out Memories" (PDF). The Aerospace Corporation. Archived (PDF) from the original on 2018-03-14.

tmdn.org

"EEPROM". TMview. Archived from the original on 2018-03-10.

usenix.org

static.usenix.org

Gutmann, Peter (2001-08-15). "Data Remanence in Semiconductor Devices". 10th USENIX SECURITY SYMPOSIUM. IBM T. J. Watson Research Center: 39–54. Archived from the original on 2016-10-12.

uspto.gov

pdfpiw.uspto.gov

Abbas, Shakir A.; Barile, Conrad A.; Lane, Ralph D.; Liu., Peter T (1973-03-16). "US3836992A; Electrically erasable floating gate fet memory cell". pdfpiw.uspto.gov. United States Patent and Trademark Office. Archived from the original on 2018-03-09.

web.archive.org

"TN-04-42: Memory Module Serial Presence-Detect" (PDF). Micron Technology. 2002. Archived from the original (PDF) on 2022-07-26. Retrieved 2020-10-11.
Tarui, Yasuo; Nagai, Kiyoko; Hayashi, Yutaka (1974-07-19). "Nonvolatile Semiconductor Memory" (PDF). Oyo Buturi. 43 (10): 990–1002. doi:10.11470/oubutsu1932.43.990. ISSN 2188-2290. Archived (PDF) from the original on 2018-03-12.
"EEPROM". TMview. Archived from the original on 2018-03-10.
Rai, Yasuki; Sasami, Terutoshi; Hasegawa, Yuzuru; Okazoe, Masaru (1973-05-18). "Electrically reprogrammable nonvolatile floating gate semi-conductor memory device and method of operation". Archived from the original on 2018-05-03. {{cite journal}}: Cite journal requires |journal= (help)
Abbas, Shakir A.; Barile, Conrad A.; Lane, Ralph D.; Liu., Peter T (1973-03-16). "US3836992A; Electrically erasable floating gate fet memory cell". pdfpiw.uspto.gov. United States Patent and Trademark Office. Archived from the original on 2018-03-09.
"Seeq Technology » AntiqueTech". Archived from the original on 2014-10-02.
Rostky, George (July 2, 2002). "Remembering the PROM knights of Intel". EE Times. Archived from the original on September 29, 2007. Retrieved 2007-02-08.
Atmel AT28C16 datasheet (PDF) (0540B ed.). October 1998. Archived (PDF) from the original on 2017-08-29.
Gutmann, Peter (2001-08-15). "Data Remanence in Semiconductor Devices". 10th USENIX SECURITY SYMPOSIUM. IBM T. J. Watson Research Center: 39–54. Archived from the original on 2016-10-12.
Koga, R.; Tran, V.; George, J.; Crawford, K.; Crain, S.; Zakrzewski, M.; Yu, P. "SEE Sensitivities of Selected Advanced Flash and First-In-First-Out Memories" (PDF). The Aerospace Corporation. Archived (PDF) from the original on 2018-03-14.
"Breaking copy protection in microcontrollers". www.cl.cam.ac.uk. Archived from the original on 2017-10-22.
"Frequently Asked Questions -ROHM Semiconductor". Archived from the original on 2011-02-19.

wikiwix.com

archive.wikiwix.com

"1027459330501acc.pdf" (PDF). Archived (PDF) from the original on 2015-02-07. Retrieved 2015-02-05.

worldcat.org

search.worldcat.org

Tarui, Y.; Hayashi, Y.; Nagai, K. (1972). "Electrically reprogrammable nonvolatile semiconductor memory". IEEE Journal of Solid-State Circuits. 7 (5): 369–375. Bibcode:1972IJSSC...7..369T. doi:10.1109/JSSC.1972.1052895. ISSN 0018-9200.
Iizuka, H.; Masuoka, F.; Sato, Tai; Ishikawa, M. (1976). "Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure". IEEE Transactions on Electron Devices. 23 (4): 379–387. Bibcode:1976ITED...23..379I. doi:10.1109/T-ED.1976.18415. ISSN 0018-9383. S2CID 30491074.
Rossler, B. (1977). "Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell". IEEE Transactions on Electron Devices. 24 (5): 606–610. Bibcode:1977ITED...24..606R. doi:10.1109/T-ED.1977.18788. ISSN 0018-9383. S2CID 33203267.
Tarui, Yasuo; Nagai, Kiyoko; Hayashi, Yutaka (1974-07-19). "Nonvolatile Semiconductor Memory" (PDF). Oyo Buturi. 43 (10): 990–1002. doi:10.11470/oubutsu1932.43.990. ISSN 2188-2290. Archived (PDF) from the original on 2018-03-12.
Verwey, J. F.; Kramer, R. P. (1974). "Atmos—An electrically reprogrammable read-only memory device". IEEE Transactions on Electron Devices. 21 (10): 631–636. Bibcode:1974ITED...21..631V. doi:10.1109/T-ED.1974.17981. ISSN 0018-9383.
Gosney, W. M. (1977). "DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology". IEEE Transactions on Electron Devices. 24 (5): 594–599. Bibcode:1977ITED...24..594G. doi:10.1109/T-ED.1977.18786. ISSN 0018-9383. S2CID 45636024.
Chen, P. C. Y. (May 1977). "Threshold-alterable Si-gate MOS devices". IEEE Transactions on Electron Devices. 24 (5): 584–586. Bibcode:1977ITED...24..584C. doi:10.1109/T-ED.1977.18783. ISSN 0018-9383. S2CID 25586393.
Rossler, B. (May 1977). "Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell". IEEE Transactions on Electron Devices. 24 (5): 606–610. Bibcode:1977ITED...24..606R. doi:10.1109/T-ED.1977.18788. ISSN 0018-9383. S2CID 33203267.