ERC32 (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "ERC32" in English language version.

Last modified: 12:42:02, 14 June 2026 (UTC)

Ref.Un. Ref.Website

Global rank English rank

64doi.org

2^nd place

43worldcat.org

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42esa.int

1,073^rd place

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32ieee.org

912^th place

722^nd place

32computer.org

6,549^th place

4,616^th place

22adsabs.harvard.edu

14^th place

9^th place

21sciencedirect.com

137^th place

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11eetimes.com

4,224^th place

2,761^st place

11reuters.com

38^th place

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11acm.org

1,200^th place

821^st place

acm.org (Global: 1,200^th place; English: 821^st place)

dl.acm.org

Parra, Pablo; da Silva, Antonio; Losa, Borja; Ignacio García, J.; Rodríguez Polo, Óscar; Martínez, Agustín; Sánchez, Sebastián (24 July 2023). "Tailor-made Virtualization Monitor Design for CPU Virtualization on LEON Processors". ACM Transactions on Embedded Computing Systems. 22 (4) 60. Association for Computing Machinery: 5. doi:10.1145/358470. eISSN 1558-3465. Retrieved 23 March 2026. LEON is an implementation of the SPARC V8 architecture whose development was promoted by the ESA as an evolution of the ERC32 platform.

adsabs.harvard.edu (Global: 14^th place; English: 9^th place)

adsabs.harvard.edu

Corbière, T.; Gaisler, J. (July 1997). Kaldeich-Schürmann, Brigitte (ed.). ERC 32 Radiation Tolerant RISC Processor; Tolerance to Radiation. Electronic Component Conference - EECC'97, Proceedings of the 3rd ESA Electronic Component Conference held 22-25 April, 1997 at ESTEC, Noordwijk, the Netherlands. Paris: European Space Agency. Bibcode:1997ESASP.395..475C. Retrieved 23 March 2026 – via SAO/NASA Astrophysics Data System.

ui.adsabs.harvard.edu

Corbière, T.; Gaisler, J. (July 1997). Kaldeich-Schürmann, Brigitte (ed.). ERC 32 Radiation Tolerant RISC Processor; Tolerance to Radiation. Electronic Component Conference - EECC'97, Proceedings of the 3rd ESA Electronic Component Conference held 22-25 April, 1997 at ESTEC, Noordwijk, the Netherlands. Paris: European Space Agency. Bibcode:1997ESASP.395..475C. Retrieved 23 March 2026 – via SAO/NASA Astrophysics Data System.

computer.org (Global: 6,549^th place; English: 4,616^th place)

Renaud, Nicolas (6 September 2005) [6-8 July 2005]. How to Cope with SEU/SET at Chip Level? The Example of a Microprocessor Family. 11th IEEE International On-Line Testing Symposium. Institute of Electrical and Electronics Engineers. p. 313. doi:10.1109/IOLTS.2005.33. ISBN 0-7695-2406-0. ISSN 1530-1591. Retrieved 23 March 2026 – via IEEE Xplore. ...a SPARC processor product line for space has been made available by ATMEL since now more than ten years, starting by the ERC32 three chips processor and followed by the TSC695F ERC32 single chip processor.
Pouponnot, A.L.R. (6 September 2005) [6-8 July 2005]. Strategic use of SEE mitigation techniques for the development of the ESA microprocessors: past, present, and future. 11th IEEE International On-Line Testing Symposium. p. 320. doi:10.1109/IOLTS.2005.66. ISBN 0-7695-2406-0. ISSN 1942-9401. Retrieved 23 March 2026 – via IEEE Xplore.

doi.org (Global: 2^nd place; English: 2^nd place)

Gorbunov, M.S. (11 April 2019). "Design of fault-tolerant microprocessors for space applications". Acta Astronautica. 163 (Part A) (published October 2019). doi:10.1016/j.actaastro.2019.04.029. Retrieved 23 March 2026 – via Science Direct. The first chip was SPARC V7 ERC32 32-bit microprocessor designed by Gaisler Research AB (now Cobham Gaisler AB) and manufactured by Temic GmbH (now Atmel).
Renaud, Nicolas (6 September 2005) [6-8 July 2005]. How to Cope with SEU/SET at Chip Level? The Example of a Microprocessor Family. 11th IEEE International On-Line Testing Symposium. Institute of Electrical and Electronics Engineers. p. 313. doi:10.1109/IOLTS.2005.33. ISBN 0-7695-2406-0. ISSN 1530-1591. Retrieved 23 March 2026 – via IEEE Xplore. ...a SPARC processor product line for space has been made available by ATMEL since now more than ten years, starting by the ERC32 three chips processor and followed by the TSC695F ERC32 single chip processor.
Pouponnot, A.L.R. (6 September 2005) [6-8 July 2005]. Strategic use of SEE mitigation techniques for the development of the ESA microprocessors: past, present, and future. 11th IEEE International On-Line Testing Symposium. p. 320. doi:10.1109/IOLTS.2005.66. ISBN 0-7695-2406-0. ISSN 1942-9401. Retrieved 23 March 2026 – via IEEE Xplore.
Parra, Pablo; da Silva, Antonio; Losa, Borja; Ignacio García, J.; Rodríguez Polo, Óscar; Martínez, Agustín; Sánchez, Sebastián (24 July 2023). "Tailor-made Virtualization Monitor Design for CPU Virtualization on LEON Processors". ACM Transactions on Embedded Computing Systems. 22 (4) 60. Association for Computing Machinery: 5. doi:10.1145/358470. eISSN 1558-3465. Retrieved 23 March 2026. LEON is an implementation of the SPARC V8 architecture whose development was promoted by the ESA as an evolution of the ERC32 platform.

eetimes.com (Global: 4,224^th place; English: 2,761^st place)

"Atmel Acquires Temic Semiconductor's Integrated Circuit Business". EE Times. 9 March 1998. Retrieved 23 March 2026.

esa.int (Global: 1,073^rd place; English: 1,115^th place)

microelectronics.esa.int

"ERC32". European Space Research and Technology Centre. 31 October 2011. Retrieved 23 March 2026.

esa.int

"Overview of LEON tools". European Space Agency. 11 November 2009. Retrieved 23 March 2026. The LEON is ERC32's successor and is the latest iteration of ESA's effort in providing a source of radiation tolerant microprocessors to the European space industry.

ieee.org (Global: 912^th place; English: 722^nd place)

ieeexplore.ieee.org

Renaud, Nicolas (6 September 2005) [6-8 July 2005]. How to Cope with SEU/SET at Chip Level? The Example of a Microprocessor Family. 11th IEEE International On-Line Testing Symposium. Institute of Electrical and Electronics Engineers. p. 313. doi:10.1109/IOLTS.2005.33. ISBN 0-7695-2406-0. ISSN 1530-1591. Retrieved 23 March 2026 – via IEEE Xplore. ...a SPARC processor product line for space has been made available by ATMEL since now more than ten years, starting by the ERC32 three chips processor and followed by the TSC695F ERC32 single chip processor.
Pouponnot, A.L.R. (6 September 2005) [6-8 July 2005]. Strategic use of SEE mitigation techniques for the development of the ESA microprocessors: past, present, and future. 11th IEEE International On-Line Testing Symposium. p. 320. doi:10.1109/IOLTS.2005.66. ISBN 0-7695-2406-0. ISSN 1942-9401. Retrieved 23 March 2026 – via IEEE Xplore.

reuters.com (Global: 38^th place; English: 30^th place)

"Microchip Technology completes Atmel acquisition". Reuters. 4 April 2016. Retrieved 23 March 2026.

sciencedirect.com (Global: 137^th place; English: 146^th place)

Gorbunov, M.S. (11 April 2019). "Design of fault-tolerant microprocessors for space applications". Acta Astronautica. 163 (Part A) (published October 2019). doi:10.1016/j.actaastro.2019.04.029. Retrieved 23 March 2026 – via Science Direct. The first chip was SPARC V7 ERC32 32-bit microprocessor designed by Gaisler Research AB (now Cobham Gaisler AB) and manufactured by Temic GmbH (now Atmel).

worldcat.org (Global: 4^th place; English: 4^th place)

search.worldcat.org

Renaud, Nicolas (6 September 2005) [6-8 July 2005]. How to Cope with SEU/SET at Chip Level? The Example of a Microprocessor Family. 11th IEEE International On-Line Testing Symposium. Institute of Electrical and Electronics Engineers. p. 313. doi:10.1109/IOLTS.2005.33. ISBN 0-7695-2406-0. ISSN 1530-1591. Retrieved 23 March 2026 – via IEEE Xplore. ...a SPARC processor product line for space has been made available by ATMEL since now more than ten years, starting by the ERC32 three chips processor and followed by the TSC695F ERC32 single chip processor.
Pouponnot, A.L.R. (6 September 2005) [6-8 July 2005]. Strategic use of SEE mitigation techniques for the development of the ESA microprocessors: past, present, and future. 11th IEEE International On-Line Testing Symposium. p. 320. doi:10.1109/IOLTS.2005.66. ISBN 0-7695-2406-0. ISSN 1942-9401. Retrieved 23 March 2026 – via IEEE Xplore.
Parra, Pablo; da Silva, Antonio; Losa, Borja; Ignacio García, J.; Rodríguez Polo, Óscar; Martínez, Agustín; Sánchez, Sebastián (24 July 2023). "Tailor-made Virtualization Monitor Design for CPU Virtualization on LEON Processors". ACM Transactions on Embedded Computing Systems. 22 (4) 60. Association for Computing Machinery: 5. doi:10.1145/358470. eISSN 1558-3465. Retrieved 23 March 2026. LEON is an implementation of the SPARC V8 architecture whose development was promoted by the ESA as an evolution of the ERC32 platform.

ERC32 (English Wikipedia)

acm.org (Global: 1,200th place; English: 821st place)

dl.acm.org

adsabs.harvard.edu (Global: 14th place; English: 9th place)

adsabs.harvard.edu

ui.adsabs.harvard.edu

computer.org (Global: 6,549th place; English: 4,616th place)

doi.org (Global: 2nd place; English: 2nd place)

eetimes.com (Global: 4,224th place; English: 2,761st place)

esa.int (Global: 1,073rd place; English: 1,115th place)