Fin field-effect transistor (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Fin field-effect transistor" in English language version.

refsWebsite

Global rank English rank

16doi.org

2^nd place

11semanticscholar.org

11^th place

8^th place

7web.archive.org

1^st place

5harvard.edu

18^th place

17^th place

3worldcat.org

5^th place

3intel.com

1,118^th place

825^th place

2anandtech.com

1,383^rd place

878^th place

2berkeley.edu

580^th place

462^nd place

2wsu.edu

3,088^th place

2,250^th place

2psu.edu

207^th place

136^th place

2handle.net

102^nd place

76^th place

2tsmc.com

low place

2ieee.org

652^nd place

515^th place

1jestr.org

low place

1computerhope.com

8,400^th place

6,430^th place

1semiwiki.com

low place

1books.google.com

3^rd place

1highbeam.com

405^th place

256^th place

1rice.edu

3,843^rd place

2,772^nd place

1techradar.com

1,521^st place

944^th place

1skhynix.com

low place

1tomshardware.co.uk

low place

1tomshardware.com

2,976^th place

1,939^th place

1eetimes.com

3,722^nd place

2,509^th place

anandtech.com

Shimpi, Anand Lal (4 May 2011). "Intel Announces first 22nm 3D Tri-Gate Transistors, Shipping in 2H 2011". AnandTech. Retrieved 18 January 2022.
Shilov, Anton. "Samsung Completes Development of 5nm EUV Process Technology". www.anandtech.com. Retrieved 2019-05-31.

berkeley.edu

people.eecs.berkeley.edu

Tsu-Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". University of California, Berkeley. Symposium on VLSI Technology Short Course. Archived from the original on 28 May 2016. Retrieved 9 July 2019.
Hisamoto, Digh; Hu, Chenming; Huang, Xuejue; Lee, Wen-Chin; Kuo, Charles; et al. (May 2001). "Sub-50 nm P-channel FinFET" (PDF). IEEE Transactions on Electron Devices. 48 (5): 880–886. Bibcode:2001ITED...48..880H. doi:10.1109/16.918235.

books.google.com

Colinge, J. P. (2008). FinFETs and Other Multi-Gate Transistors. Springer Science & Business Media. pp. 11 & 39. ISBN 9780387717517.

computerhope.com

"What is Finfet?". Computer Hope. April 26, 2017. Retrieved 4 July 2019.

doi.org

Kamal, Kamal Y. (2022). "The Silicon Age: Trends in Semiconductor Devices Industry" (PDF). Journal of Engineering Science and Technology Review. 15 (1): 110–115. doi:10.25103/jestr.151.14. ISSN 1791-2377. S2CID 249074588. Retrieved 2022-05-26.
Farrah, H. R.; Steinberg, R. F. (February 1967). "Analysis of double-gate thin-film transistor". IEEE Transactions on Electron Devices. 14 (2): 69–74. Bibcode:1967ITED...14...69F. doi:10.1109/T-ED.1967.15901.
Sekigawa, Toshihiro; Hayashi, Yutaka (August 1984). "Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate". Solid-State Electronics. 27 (8): 827–828. Bibcode:1984SSEle..27..827S. doi:10.1016/0038-1101(84)90036-4. ISSN 0038-1101.
Hisamoto, Digh; Kaga, Toru; Kawamoto, Yoshifumi; Takeda, Eiji (December 1989). "A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET". International Technical Digest on Electron Devices Meeting. pp. 833–836. doi:10.1109/IEDM.1989.74182. S2CID 114072236.
Leobandung, Effendi; Chou, Stephen Y. (1996). "Reduction of short channel effects in SOI MOSFETs with 35 nm channel width and 70 nm channel length". 1996 54th Annual Device Research Conference Digest. pp. 110–111. doi:10.1109/DRC.1996.546334. ISBN 0-7803-3358-6. S2CID 30066882.
Leobandung, Effendi; Gu, Jian; Guo, Lingjie; Chou, Stephen Y. (1997-11-01). "Wire-channel and wrap-around-gate metal–oxide–semiconductor field-effect transistors with a significant reduction of short channel effects". Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena. 15 (6): 2791–2794. Bibcode:1997JVSTB..15.2791L. doi:10.1116/1.589729. ISSN 1071-1023.
Hisamoto, Digh; Hu, Chenming; Liu, Tsu-Jae King; Bokor, Jeffrey; Lee, Wen-Chin; Kedzierski, Jakub; Anderson, Erik; Takeuchi, Hideki; Asano, Kazuya (December 1998). "A folded-channel MOSFET for deep-sub-tenth micron era". International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217). pp. 1032–1034. doi:10.1109/IEDM.1998.746531. ISBN 0-7803-4774-9. S2CID 37774589.
Hisamoto, Digh; Kedzierski, Jakub; Anderson, Erik; Takeuchi, Hideki (December 1999). "Sub 50-nm FinFET: PMOS" (PDF). International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318). pp. 67–70. doi:10.1109/IEDM.1999.823848. ISBN 0-7803-5410-9. S2CID 7310589. Archived from the original (PDF) on 2010-06-06. Retrieved 2019-09-25.
Hu, Chenming; Choi, Yang-Kyu; Lindert, N.; Xuan, P.; Tang, S.; Ha, D.; Anderson, E.; Bokor, J.; Tsu-Jae King, Liu (December 2001). "Sub-20 nm CMOS FinFET technologies". International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224). pp. 19.1.1–19.1.4. doi:10.1109/IEDM.2001.979526. ISBN 0-7803-7050-3. S2CID 8908553.
Ahmed, Shibly; Bell, Scott; Tabery, Cyrus; Bokor, Jeffrey; Kyser, David; Hu, Chenming; Liu, Tsu-Jae King; Yu, Bin; Chang, Leland (December 2002). "FinFET scaling to 10 nm gate length" (PDF). Digest. International Electron Devices Meeting. pp. 251–254. CiteSeerX 10.1.1.136.3757. doi:10.1109/IEDM.2002.1175825. ISBN 0-7803-7462-2. S2CID 7106946. Archived from the original (PDF) on 2020-05-27. Retrieved 2019-09-25.
Hisamoto, Digh; Hu, Chenming; Bokor, J.; King, Tsu-Jae; Anderson, E.; et al. (December 2000). "FinFET—a self-aligned double-gate MOSFET scalable to 20 nm". IEEE Transactions on Electron Devices. 47 (12): 2320–2325. Bibcode:2000ITED...47.2320H. CiteSeerX 10.1.1.211.204. doi:10.1109/16.887014.
Hisamoto, Digh; Hu, Chenming; Huang, Xuejue; Lee, Wen-Chin; Kuo, Charles; et al. (May 2001). "Sub-50 nm P-channel FinFET" (PDF). IEEE Transactions on Electron Devices. 48 (5): 880–886. Bibcode:2001ITED...48..880H. doi:10.1109/16.918235.
Lee, Hyunjin; et al. (2006). "Sub-5nm All-Around Gate FinFET for Ultimate Scaling". 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers. pp. 58–59. doi:10.1109/VLSIT.2006.1705215. hdl:10203/698. ISBN 978-1-4244-0005-8. S2CID 26482358.
Rostami, M.; Mohanram, K. (2011). "Dual-V_th Independent-Gate FinFETs for Low Power Logic Circuits" (PDF). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30 (3): 337–349. doi:10.1109/TCAD.2010.2097310. hdl:1911/72088. S2CID 2225579.
Bohr, Mark T.; Young, Ian A. (2017). "CMOS Scaling Trends and Beyond". IEEE Micro. 37 (6): 20–29. doi:10.1109/MM.2017.4241347. S2CID 6700881. The next major transistor innovation was the introduction of FinFET (tri-gate) transistors on Intel's 22-nm technology in 2011.

dx.doi.org

Leobandung, Effendi; Gu, Jian; Guo, Lingjie; Chou, Stephen Y. (1997-11-01). "Wire-channel and wrap-around-gate metal–oxide–semiconductor field-effect transistors with a significant reduction of short channel effects". Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena. 15 (6): 2791–2794. Bibcode:1997JVSTB..15.2791L. doi:10.1116/1.589729. ISSN 1071-1023.

eetimes.com

"Samsung, GF Ramp FD-SOI". 27 April 2018.

handle.net

hdl.handle.net

Lee, Hyunjin; et al. (2006). "Sub-5nm All-Around Gate FinFET for Ultimate Scaling". 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers. pp. 58–59. doi:10.1109/VLSIT.2006.1705215. hdl:10203/698. ISBN 978-1-4244-0005-8. S2CID 26482358.
Rostami, M.; Mohanram, K. (2011). "Dual-V_th Independent-Gate FinFETs for Low Power Logic Circuits" (PDF). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30 (3): 337–349. doi:10.1109/TCAD.2010.2097310. hdl:1911/72088. S2CID 2225579.

harvard.edu

ui.adsabs.harvard.edu

Farrah, H. R.; Steinberg, R. F. (February 1967). "Analysis of double-gate thin-film transistor". IEEE Transactions on Electron Devices. 14 (2): 69–74. Bibcode:1967ITED...14...69F. doi:10.1109/T-ED.1967.15901.
Sekigawa, Toshihiro; Hayashi, Yutaka (August 1984). "Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate". Solid-State Electronics. 27 (8): 827–828. Bibcode:1984SSEle..27..827S. doi:10.1016/0038-1101(84)90036-4. ISSN 0038-1101.
Leobandung, Effendi; Gu, Jian; Guo, Lingjie; Chou, Stephen Y. (1997-11-01). "Wire-channel and wrap-around-gate metal–oxide–semiconductor field-effect transistors with a significant reduction of short channel effects". Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena. 15 (6): 2791–2794. Bibcode:1997JVSTB..15.2791L. doi:10.1116/1.589729. ISSN 1071-1023.
Hisamoto, Digh; Hu, Chenming; Bokor, J.; King, Tsu-Jae; Anderson, E.; et al. (December 2000). "FinFET—a self-aligned double-gate MOSFET scalable to 20 nm". IEEE Transactions on Electron Devices. 47 (12): 2320–2325. Bibcode:2000ITED...47.2320H. CiteSeerX 10.1.1.211.204. doi:10.1109/16.887014.
Hisamoto, Digh; Hu, Chenming; Huang, Xuejue; Lee, Wen-Chin; Kuo, Charles; et al. (May 2001). "Sub-50 nm P-channel FinFET" (PDF). IEEE Transactions on Electron Devices. 48 (5): 880–886. Bibcode:2001ITED...48..880H. doi:10.1109/16.918235.

highbeam.com

"Still Room at the Bottom.(nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )", Nanoparticle News, 1 April 2006, archived from the original on 6 November 2012, retrieved 6 July 2019

ieee.org

"IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers. Archived from the original on September 9, 2018. Retrieved 4 July 2019.

spectrum.ieee.org

"How the Father of FinFETs Helped Save Moore's Law: Chenming Hu, the 2020 IEEE Medal of Honor recipient, took transistors into the third dimension". IEEE Spectrum. 21 April 2020. Retrieved 27 December 2021.

intel.com

"The Breakthrough Advantage for FPGAs with Tri-Gate Technology" (PDF). Intel. 2014. Retrieved 4 July 2019.

download.intel.com

Bohr, Mark; Mistry, Kaizad (May 2011). "Intel's Revolutionary 22 nm Transistor Technology" (PDF). intel.com. Retrieved April 18, 2018.

newsroom.intel.com

"Intel 22nm 3-D Tri-Gate Transistor Technology". Intel Newsroom.

jestr.org

Kamal, Kamal Y. (2022). "The Silicon Age: Trends in Semiconductor Devices Industry" (PDF). Journal of Engineering Science and Technology Review. 15 (1): 110–115. doi:10.25103/jestr.151.14. ISSN 1791-2377. S2CID 249074588. Retrieved 2022-05-26.

psu.edu

citeseerx.ist.psu.edu

Ahmed, Shibly; Bell, Scott; Tabery, Cyrus; Bokor, Jeffrey; Kyser, David; Hu, Chenming; Liu, Tsu-Jae King; Yu, Bin; Chang, Leland (December 2002). "FinFET scaling to 10 nm gate length" (PDF). Digest. International Electron Devices Meeting. pp. 251–254. CiteSeerX 10.1.1.136.3757. doi:10.1109/IEDM.2002.1175825. ISBN 0-7803-7462-2. S2CID 7106946. Archived from the original (PDF) on 2020-05-27. Retrieved 2019-09-25.
Hisamoto, Digh; Hu, Chenming; Bokor, J.; King, Tsu-Jae; Anderson, E.; et al. (December 2000). "FinFET—a self-aligned double-gate MOSFET scalable to 20 nm". IEEE Transactions on Electron Devices. 47 (12): 2320–2325. Bibcode:2000ITED...47.2320H. CiteSeerX 10.1.1.211.204. doi:10.1109/16.887014.

rice.edu

scholarship.rice.edu

Rostami, M.; Mohanram, K. (2011). "Dual-V_th Independent-Gate FinFETs for Low Power Logic Circuits" (PDF). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30 (3): 337–349. doi:10.1109/TCAD.2010.2097310. hdl:1911/72088. S2CID 2225579.

semanticscholar.org

api.semanticscholar.org

Kamal, Kamal Y. (2022). "The Silicon Age: Trends in Semiconductor Devices Industry" (PDF). Journal of Engineering Science and Technology Review. 15 (1): 110–115. doi:10.25103/jestr.151.14. ISSN 1791-2377. S2CID 249074588. Retrieved 2022-05-26.
Koike, Hanpei; Nakagawa, Tadashi; Sekigawa, Toshiro; Suzuki, E.; Tsutsumi, Toshiyuki (23 February 2003). "Primary Consideration on Compact Modeling of DG MOSFETs with Four-terminal Operation Mode". TechConnect Briefs. 2 (2003): 330–333. S2CID 189033174.
Hisamoto, Digh; Kaga, Toru; Kawamoto, Yoshifumi; Takeda, Eiji (December 1989). "A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET". International Technical Digest on Electron Devices Meeting. pp. 833–836. doi:10.1109/IEDM.1989.74182. S2CID 114072236.
Leobandung, Effendi; Chou, Stephen Y. (1996). "Reduction of short channel effects in SOI MOSFETs with 35 nm channel width and 70 nm channel length". 1996 54th Annual Device Research Conference Digest. pp. 110–111. doi:10.1109/DRC.1996.546334. ISBN 0-7803-3358-6. S2CID 30066882.
Hisamoto, Digh; Hu, Chenming; Liu, Tsu-Jae King; Bokor, Jeffrey; Lee, Wen-Chin; Kedzierski, Jakub; Anderson, Erik; Takeuchi, Hideki; Asano, Kazuya (December 1998). "A folded-channel MOSFET for deep-sub-tenth micron era". International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217). pp. 1032–1034. doi:10.1109/IEDM.1998.746531. ISBN 0-7803-4774-9. S2CID 37774589.
Hisamoto, Digh; Kedzierski, Jakub; Anderson, Erik; Takeuchi, Hideki (December 1999). "Sub 50-nm FinFET: PMOS" (PDF). International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318). pp. 67–70. doi:10.1109/IEDM.1999.823848. ISBN 0-7803-5410-9. S2CID 7310589. Archived from the original (PDF) on 2010-06-06. Retrieved 2019-09-25.
Hu, Chenming; Choi, Yang-Kyu; Lindert, N.; Xuan, P.; Tang, S.; Ha, D.; Anderson, E.; Bokor, J.; Tsu-Jae King, Liu (December 2001). "Sub-20 nm CMOS FinFET technologies". International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224). pp. 19.1.1–19.1.4. doi:10.1109/IEDM.2001.979526. ISBN 0-7803-7050-3. S2CID 8908553.
Ahmed, Shibly; Bell, Scott; Tabery, Cyrus; Bokor, Jeffrey; Kyser, David; Hu, Chenming; Liu, Tsu-Jae King; Yu, Bin; Chang, Leland (December 2002). "FinFET scaling to 10 nm gate length" (PDF). Digest. International Electron Devices Meeting. pp. 251–254. CiteSeerX 10.1.1.136.3757. doi:10.1109/IEDM.2002.1175825. ISBN 0-7803-7462-2. S2CID 7106946. Archived from the original (PDF) on 2020-05-27. Retrieved 2019-09-25.
Lee, Hyunjin; et al. (2006). "Sub-5nm All-Around Gate FinFET for Ultimate Scaling". 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers. pp. 58–59. doi:10.1109/VLSIT.2006.1705215. hdl:10203/698. ISBN 978-1-4244-0005-8. S2CID 26482358.
Rostami, M.; Mohanram, K. (2011). "Dual-V_th Independent-Gate FinFETs for Low Power Logic Circuits" (PDF). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30 (3): 337–349. doi:10.1109/TCAD.2010.2097310. hdl:1911/72088. S2CID 2225579.
Bohr, Mark T.; Young, Ian A. (2017). "CMOS Scaling Trends and Beyond". IEEE Micro. 37 (6): 20–29. doi:10.1109/MM.2017.4241347. S2CID 6700881. The next major transistor innovation was the introduction of FinFET (tri-gate) transistors on Intel's 22-nm technology in 2011.

semiwiki.com

"VLSI Symposium - TSMC and Imec on Advanced Process and Devices Technology Toward 2nm". 25 February 2024.

skhynix.com

"History: 2010s". SK Hynix. Archived from the original on 17 May 2021. Retrieved 8 July 2019.

techradar.com

Grabham, Dan (May 6, 2011). "Intel's Tri-Gate transistors: everything you need to know". TechRadar. Retrieved April 19, 2018.

tomshardware.co.uk

"Samsung Mass Producing 128Gb 3-bit MLC NAND Flash". Tom's Hardware. 11 April 2013. Archived from the original on 21 June 2019. Retrieved 21 June 2019.

tomshardware.com

Armasu, Lucian (11 January 2019), "Samsung Plans Mass Production of 3nm GAAFET Chips in 2021", www.tomshardware.com

tsmc.com

"16/12nm Technology". TSMC. Retrieved 30 June 2019.
"7nm Technology". TSMC. Retrieved 30 June 2019.

web.archive.org

"IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers. Archived from the original on September 9, 2018. Retrieved 4 July 2019.
Tsu-Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". University of California, Berkeley. Symposium on VLSI Technology Short Course. Archived from the original on 28 May 2016. Retrieved 9 July 2019.
Hisamoto, Digh; Kedzierski, Jakub; Anderson, Erik; Takeuchi, Hideki (December 1999). "Sub 50-nm FinFET: PMOS" (PDF). International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318). pp. 67–70. doi:10.1109/IEDM.1999.823848. ISBN 0-7803-5410-9. S2CID 7310589. Archived from the original (PDF) on 2010-06-06. Retrieved 2019-09-25.
Ahmed, Shibly; Bell, Scott; Tabery, Cyrus; Bokor, Jeffrey; Kyser, David; Hu, Chenming; Liu, Tsu-Jae King; Yu, Bin; Chang, Leland (December 2002). "FinFET scaling to 10 nm gate length" (PDF). Digest. International Electron Devices Meeting. pp. 251–254. CiteSeerX 10.1.1.136.3757. doi:10.1109/IEDM.2002.1175825. ISBN 0-7803-7462-2. S2CID 7106946. Archived from the original (PDF) on 2020-05-27. Retrieved 2019-09-25.
"Still Room at the Bottom.(nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )", Nanoparticle News, 1 April 2006, archived from the original on 6 November 2012, retrieved 6 July 2019
"History: 2010s". SK Hynix. Archived from the original on 17 May 2021. Retrieved 8 July 2019.
"Samsung Mass Producing 128Gb 3-bit MLC NAND Flash". Tom's Hardware. 11 April 2013. Archived from the original on 21 June 2019. Retrieved 21 June 2019.

worldcat.org

search.worldcat.org

Kamal, Kamal Y. (2022). "The Silicon Age: Trends in Semiconductor Devices Industry" (PDF). Journal of Engineering Science and Technology Review. 15 (1): 110–115. doi:10.25103/jestr.151.14. ISSN 1791-2377. S2CID 249074588. Retrieved 2022-05-26.
Sekigawa, Toshihiro; Hayashi, Yutaka (August 1984). "Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate". Solid-State Electronics. 27 (8): 827–828. Bibcode:1984SSEle..27..827S. doi:10.1016/0038-1101(84)90036-4. ISSN 0038-1101.
Leobandung, Effendi; Gu, Jian; Guo, Lingjie; Chou, Stephen Y. (1997-11-01). "Wire-channel and wrap-around-gate metal–oxide–semiconductor field-effect transistors with a significant reduction of short channel effects". Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena. 15 (6): 2791–2794. Bibcode:1997JVSTB..15.2791L. doi:10.1116/1.589729. ISSN 1071-1023.

wsu.edu

eecs.wsu.edu

Hisamoto, Digh; Kedzierski, Jakub; Anderson, Erik; Takeuchi, Hideki (December 1999). "Sub 50-nm FinFET: PMOS" (PDF). International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318). pp. 67–70. doi:10.1109/IEDM.1999.823848. ISBN 0-7803-5410-9. S2CID 7310589. Archived from the original (PDF) on 2010-06-06. Retrieved 2019-09-25.
Ahmed, Shibly; Bell, Scott; Tabery, Cyrus; Bokor, Jeffrey; Kyser, David; Hu, Chenming; Liu, Tsu-Jae King; Yu, Bin; Chang, Leland (December 2002). "FinFET scaling to 10 nm gate length" (PDF). Digest. International Electron Devices Meeting. pp. 251–254. CiteSeerX 10.1.1.136.3757. doi:10.1109/IEDM.2002.1175825. ISBN 0-7803-7462-2. S2CID 7106946. Archived from the original (PDF) on 2020-05-27. Retrieved 2019-09-25.