Floorplan (microelectronics) (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Floorplan (microelectronics)" in English language version.

refsWebsite

Global rank English rank

8doi.org

2^nd place

1ivlsi.com

low place

1arxiv.org

69^th place

59^th place

1medium.com

551^st place

406^th place

1vlsitalks.com

low place

1ieee.org

652^nd place

515^th place

arxiv.org (Global: 69^th place; English: 59^th place)

Liu, Chen-Wei and Chang, Yao-Wen (2024-09-01). "Physical Design: Methodologies and Developments". arXiv:2409.04726 [eess.SY].{{cite arXiv}}: CS1 maint: multiple names: authors list (link)

doi.org (Global: 2^nd place; English: 2^nd place)

Kahng, Andrew B. (2000). "Classical floorplanning harmful?". Proceedings of the 2000 international symposium on Physical design. ISPD '00. Association for Computing Machinery. pp. 207–213. doi:10.1145/332357.332401. ISBN 1-58113-191-7. Retrieved 2025-06-12.
Lin, Ruei-Bin; Chiang, Yi-Xiu (2019). Impact of Double-Row Height Standard Cells on Placement and Routing. 20th International Symposium on Quality Electronic Design (ISQED). Santa Clara, CA, USA: IEEE. pp. 317–322. doi:10.1109/ISQED.2019.8697712. Retrieved 2025-06-12.
Liu, Chen-Wei; Chang, Yao-Wen (2006). Floorplan and power/ground network co-synthesis for fast design convergence. 2006 International Symposium on Physical Design. ISPD '06. San Jose, California, USA: Association for Computing Machinery. pp. 86–93. doi:10.1145/1123008.1123026. Retrieved 2025-06-12.
Funke, Julia; Hougardy, Stefan; Schneider, Jan (2016). "An exact algorithm for wirelength optimal placements in VLSI design". Integration: The VLSI Journal. 52: 355–366. doi:10.1016/j.vlsi.2015.07.001. Retrieved 2025-06-12.
Silvanus, Jannik; Vygen, Jens (2017). "Few Sequence Pairs Suffice: Representing All Rectangle Placements". SIAM Journal on Discrete Mathematics. 34: 2017–2032. doi:10.1137/16M1095880 (inactive 1 July 2025).{{cite journal}}: CS1 maint: DOI inactive as of July 2025 (link)
Tang, M.; Sebastian, A. (2005). "A Genetic Algorithm for VLSI Floorplanning Using O-Tree Representation". Applications of Evolutionary Computing. Lecture Notes in Computer Science. Vol. 3449. Springer Berlin Heidelberg. pp. 215–224. doi:10.1007/978-3-540-32003-6_22.
Fernando, J.; Katkoori, S. (2008). "An Elitist Non-dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning". Proceedings of the 21st International Conference on VLSI Design. IEEE. pp. 337–342. doi:10.1109/VLSI.2008.56.
Lin, P.-H.; Chang, Y.-W.; Lin, S.-C. (2009). "Analog Placement Based on Symmetry-Island Formulation". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28 (6). IEEE: 791–804. doi:10.1109/TCAD.2009.2015708 (inactive 1 July 2025).{{cite journal}}: CS1 maint: DOI inactive as of July 2025 (link)

ieee.org (Global: 652^nd place; English: 515^th place)

ieeexplore.ieee.org

Sarrafzadeh, M, "Transforming an arbitrary floorplan into a sliceable one", Proc. 1993 IEEE/ACM International Conference on Computer-Aided Design (ICCAD-93), pp. 386-389.

ivlsi.com (Global: low place; English: low place)

"Floorplan in VLSI Physical Design". iVLSI Technologies. Retrieved 2025-06-12.

medium.com (Global: 551^st place; English: 406^th place)

VLSIPD4 (2023-04-23). "Floorplanning in Physical Design". Medium. Retrieved 2025-06-06.{{cite web}}: CS1 maint: numeric names: authors list (link)

vlsitalks.com (Global: low place; English: low place)

VLSI‑Talks (January 2023). "FLOORPLAN - VLSI TALKS". VLSI TALKS. Retrieved 2025-06-12.

Floorplan (microelectronics) (English Wikipedia)

arxiv.org (Global: 69th place; English: 59th place)

doi.org (Global: 2nd place; English: 2nd place)

ieee.org (Global: 652nd place; English: 515th place)