Gate array (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Gate array" in English language version.

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  • Pearson, Ed; Bethel, Cindy L. (April 2016). "A design review: Concepts for mitigating SQL injection attacks". 2016 4th International Symposium on Digital Forensic and Security (ISDFS). IEEE. p. 169. doi:10.1109/isdfs.2016.7473537. ISBN 978-1-4673-9865-7.
  • Seitz, Frederick (1982). "Historical overview of semiconductors". Proceedings of the IEEE. 70 (5): 516–547. doi:10.1109/PROC.1982.12345.

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  • Amerson, F.C. (September 1985). "Simplicity in a Microcoded Computer Architecture" (PDF). Hewlett Packard Journal. 36 (9): 7–12. The Series 37 CPU chip is a CMOS gate array using nearly 8000 gates.
  • Watkins, J.E.; Brown, P.A.; Szeman, G.; Carrie, S.E. (August 1984). "Hardware Design of the HP 150 Personal Computer...it's really two products — a computer and a terminal" (PDF). Hewlett Packard Journal. 35 (8): 25–30. To reduce the IC count on the video card, a PLA (programmable logic array) and a TTL gate array are used. The gate array implements most of the circuitry of the graphics controller section, including control of the RAM. Compared to discrete circuitry, the gate array consumes one fifth the space, one fourth the power, and one half the cost.
  • Bening, L.C.; Brewer, T.M.; Foster, H.D.; Quigley, J.S.; Sussman, R.A.; Vogel, P.F.; Wells, A.W. (1997). "Physical Design of 0.35-μm Gate Arrays for Symmetric Multiprocessing Servers" (PDF). Hewlett-Packard Journal. 48 (2): 95–103. The PA 8000s will initially run at 180 MHz, with the rest of the system running at 120 MHz. Except for the PA 8000 and associated SRAMs and DRAMs, the bulk of the system logic is implemented in Fujitsu CG61 0.35-μm gate arrays, as shown in Table I. (Processor Interface, Crossbar, Memory Interface, Node-to-Node Interface) One additional gate array is implemented in the much less expensive CG51 0.5-μm process. (I/O Interface)

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  • Allison, B.R.; Van Ingen, C. (1992). "Technical description of the DEC 7000 and DEC 10000 AXP family" (PDF). Digital Technical Journal. 4 (4): 100–. All modules utilize LSI Logic LCA100K series gate arrays for the system bus interface and for on-board logic functions. The LSI Logic LCA100K features up to 235K two-input NAND gates. All modules use the same custom I/O driver circuit within their respective gate arrays to drive and receive the system bus. A custom 419-pin pin grid array (PGA) package was developed to house all bus interface gate arrays. ... A minimal DEC 7000 system includes 430,000 gates of logic contained in gate arrays, whereas a minimal VAX 6000 Model 200 includes 94,000 gates.

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  • Т34ВГ1 — article about the ZX Spectrum ULA compatible chip (in Russian)

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