Integrated circuit design (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Integrated circuit design" in English language version.

refsWebsite

Global rank English rank

4doi.org

2^nd place

3semanticscholar.org

11^th place

8^th place

2semiwiki.com

low place

2springer.com

274^th place

309^th place

1quarktwin.com

low place

1theregister.com

3,700^th place

2,360^th place

1zdnet.com

786^th place

558^th place

1pcgamer.com

428^th place

286^th place

1anandtech.com

1,383^rd place

878^th place

1books.google.com

3^rd place

1ieee.org

652^nd place

515^th place

1cpushack.com

low place

1electronicdesign.com

low place

7,853^rd place

1eejournal.com

low place

1stanford.edu

179^th place

183^rd place

1arxiv.org

69^th place

59^th place

1garysmitheda.com

low place

anandtech.com

Shimpi, Anand Lal. "Inside Intel: From Silicon to the World". www.anandtech.com.

arxiv.org

Basu, Joydeep (2019-10-09). "From Design to Tape-out in SCL 180 nm CMOS Integrated Circuit Fabrication Technology". IETE Journal of Education. 60 (2): 51–64. arXiv:1908.10674. doi:10.1080/09747338.2019.1657787. S2CID 201657819.

books.google.com

Chen, Wai-Kai (3 October 2018). The VLSI Handbook. CRC Press. ISBN 978-1-4200-0596-7.

cpushack.com

"Processors to Emulate Processors: The Palladium II | the CPU Shack Museum". 21 October 2016.

doi.org

Tokuda, T.; Korematsu, J.; Shimazu, Y.; Sakashita, N.; Kengaku, T.; Fugiyama, T.; Ohno, T.; Tomisawa, O. (December 7, 1988). "A macrocell approach for VLSI processor design". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 7 (12): 1272–1277. doi:10.1109/43.16805 – via IEEE Xplore.
J. Lienig, J. Scheible (2020). "Chap. 3.3: Mask Data: Layout Post Processing". Fundamentals of Layout Design for Electronic Circuits. Springer. pp. 102–110. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. S2CID 215840278.
J. Lienig, J. Scheible (2020). "Chap. 4.6: Analog and Digital Design Flows". Fundamentals of Layout Design for Electronic Circuits. Springer. pp. 151–159. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. S2CID 215840278.
Basu, Joydeep (2019-10-09). "From Design to Tape-out in SCL 180 nm CMOS Integrated Circuit Fabrication Technology". IETE Journal of Education. 60 (2): 51–64. arXiv:1908.10674. doi:10.1080/09747338.2019.1657787. S2CID 201657819.

eejournal.com

"The First Emulators of Spring". 13 April 2021.

electronicdesign.com

"Cadence Strikes Back at Synopsys with New Circuit Simulation Tool". 21 May 2021.

garysmitheda.com

"Developments of Multi-CAD Models" (PDF). IC CAD Market Trends 2015. 2015-07-11.

ieee.org

ieeexplore.ieee.org

Tokuda, T.; Korematsu, J.; Shimazu, Y.; Sakashita, N.; Kengaku, T.; Fugiyama, T.; Ohno, T.; Tomisawa, O. (December 7, 1988). "A macrocell approach for VLSI processor design". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 7 (12): 1272–1277. doi:10.1109/43.16805 – via IEEE Xplore.

pcgamer.com

Jacob Ridley (December 26, 2022). "Inside Intel: here's what goes into making a cutting-edge gaming CPU". PC Gamer – via www.pcgamer.com.

quarktwin.com

Parker Brakus (May 17, 2022). "Analog IC: Understanding Its Importance, Functions and Applications". Quarktwin – via www.quarktwin.com.

semanticscholar.org

api.semanticscholar.org

J. Lienig, J. Scheible (2020). "Chap. 3.3: Mask Data: Layout Post Processing". Fundamentals of Layout Design for Electronic Circuits. Springer. pp. 102–110. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. S2CID 215840278.
J. Lienig, J. Scheible (2020). "Chap. 4.6: Analog and Digital Design Flows". Fundamentals of Layout Design for Electronic Circuits. Springer. pp. 151–159. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. S2CID 215840278.
Basu, Joydeep (2019-10-09). "From Design to Tape-out in SCL 180 nm CMOS Integrated Circuit Fabrication Technology". IETE Journal of Education. 60 (2): 51–64. arXiv:1908.10674. doi:10.1080/09747338.2019.1657787. S2CID 201657819.

semiwiki.com

"Cadence Introduces Palladium XP II". 18 February 2024.
"Transaction-based Emulation". 24 March 2024.

springer.com

link.springer.com

J. Lienig, J. Scheible (2020). "Chap. 3.3: Mask Data: Layout Post Processing". Fundamentals of Layout Design for Electronic Circuits. Springer. pp. 102–110. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. S2CID 215840278.
J. Lienig, J. Scheible (2020). "Chap. 4.6: Analog and Digital Design Flows". Fundamentals of Layout Design for Electronic Circuits. Springer. pp. 151–159. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. S2CID 215840278.

stanford.edu

www-group.slac.stanford.edu

https://www-group.slac.stanford.edu/ais/publicDocs/presentation137.pdf ^{[bare URL PDF]}

theregister.com

"FYI: Today's computer chips are so advanced, they are more 'mercurial' than precise – and here's the proof".

zdnet.com

"Now Google is using AI to design chips, far faster than human engineers can do the job". ZDNet.