Integrated circuit layout (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Integrated circuit layout" in English language version.

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5books.google.com

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2semanticscholar.org

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arxiv.org

Basu, Joydeep (2019-10-09). "From Design to Tape-out in SCL 180 nm CMOS Integrated Circuit Fabrication Technology". IETE Journal of Education. 60 (2): 51–64. arXiv:1908.10674. doi:10.1080/09747338.2019.1657787. S2CID 201657819.

books.google.com

Dirk Jansen, editor. "The Electronic Design Automation Handbook". 2010. p. 39.
Dan Clein. "CMOS IC Layout: Concepts, Methodologies, and Tools". 1999 p. 60.
"Conference Record". 1987. p. 118.
Charles A. Harper; Harold C. Jones. "Active Electronic Component Handbook". 1996. p. 2
Riko Radojcic. "Managing More-than-Moore Integration Technology Development". 2018. p. 99

doi.org

A. Kahng, J. Lienig, I. Markov, J. Hu: VLSI Physical Design: From Graph Partitioning to Timing Closure, doi:10.1007/978-3-030-96415-3, ISBN 978-3-030-96414-6, p. 9.
Basu, Joydeep (2019-10-09). "From Design to Tape-out in SCL 180 nm CMOS Integrated Circuit Fabrication Technology". IETE Journal of Education. 60 (2): 51–64. arXiv:1908.10674. doi:10.1080/09747338.2019.1657787. S2CID 201657819.
J. Lienig, J. Scheible (2020). "Chap. 3.3: Mask Data: Layout Post Processing". Fundamentals of Layout Design for Electronic Circuits. Springer. p. 102-110. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. S2CID 215840278.

semanticscholar.org

api.semanticscholar.org

Basu, Joydeep (2019-10-09). "From Design to Tape-out in SCL 180 nm CMOS Integrated Circuit Fabrication Technology". IETE Journal of Education. 60 (2): 51–64. arXiv:1908.10674. doi:10.1080/09747338.2019.1657787. S2CID 201657819.
J. Lienig, J. Scheible (2020). "Chap. 3.3: Mask Data: Layout Post Processing". Fundamentals of Layout Design for Electronic Circuits. Springer. p. 102-110. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. S2CID 215840278.

springer.com

link.springer.com

J. Lienig, J. Scheible (2020). "Chap. 3.3: Mask Data: Layout Post Processing". Fundamentals of Layout Design for Electronic Circuits. Springer. p. 102-110. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. S2CID 215840278.