Multi-channel memory architecture (English Wikipedia)

"BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors" (PDF). amd.com. 2013-01-11. pp. 107–108. Retrieved 2014-01-09. When the DCTs are in ganged mode, as specified by [The DRAM Controller Select Low Register] F2x110 [DctGangEn], then each logical DIMM is two channels wide. Each physical DIMM of a 2-channel logical DIMM is required to be the same size and use the same timing parameters. Both DCTs must be programmed with the same information (see 2.8.1 [DCT Configuration Registers]). When the DCTs are in unganged mode, a logical DIMM is equivalent to a 64-bit physical DIMM and each channel is controlled by a different DCT. Typical systems are recommended to run in unganged mode to benefit from the additional parallelism generated by using the DCTs independently. See 2.12.2 [DRAM Considerations for ECC] for DRAM ECC implications of ganged and unganged mode. Ganged mode is not supported for S1g3, S1g4, ASB2, and G34 processors.

anandtech.com

John H. Zurawski; John E. Murray; Paul J. Lemmon, "The Design and Verification of the AlphaStation 600 5-series Workstation", HP, 7 (1), archived from the original on 2021-02-25, retrieved 2011-10-19.

5000P memory controller, Intel.
"Core i7 Family Product Comparison". Intel. Memory Specifications: # of Memory Channels.
"Xeon Family Product Comparison". Intel. Memory Specifications: # of Memory Channels.

"Intel Dual-Channel DDR Memory Architecture White Paper" (PDF) (Rev. 1.0 ed.). Infineon Technologies North America and Kingston Technology. September 2003. Archived from the original (PDF, 1021 KB) on 2011-09-29. Retrieved 2007-09-06.

Kennedy, Patrick (23 August 2017). "Qualcomm Centriq 2400 ARM CPU from Hot Chips 29". Serve The Home. Retrieved 14 November 2017.
Kennedy, Patrick (9 November 2017). "Cavium ThunderX2 and OCP Platform Details". Serve the Home. Retrieved 14 November 2017.

Rouse, Margaret (September 2005). "JBOD (just a bunch of disks or just a bunch of drives)". SearchStorage.TechTarget.com. Retrieved 2014-01-09.

Shilov, Anton. "AMD Confirms Twelve DDR5 Memory Channels For Zen 4 EPYC CPUs". Tom's Hardware. Future US Inc. Retrieved 22 April 2024.

"Opteron 6000 Series Platform Quick Reference Guide" (PDF). AMD. Archived from the original (PDF) on 2012-05-12. Retrieved 2012-10-15.
John H. Zurawski; John E. Murray; Paul J. Lemmon, "The Design and Verification of the AlphaStation 600 5-series Workstation", HP, 7 (1), archived from the original on 2021-02-25, retrieved 2011-10-19.
"Intel Dual-Channel DDR Memory Architecture White Paper" (PDF) (Rev. 1.0 ed.). Infineon Technologies North America and Kingston Technology. September 2003. Archived from the original (PDF, 1021 KB) on 2011-09-29. Retrieved 2007-09-06.
Desktop Boards – Triple Memory Modules, Intel, archived from the original on 2009-03-08, retrieved 2011-10-01, Single- and Multichannel Memory Modes