Multigate device (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Multigate device" in English language version.

refsWebsite

Global rank English rank

16web.archive.org

1^st place

14doi.org

2^nd place

10semanticscholar.org

11^th place

8^th place

6books.google.com

3^rd place

5anandtech.com

1,383^rd place

878^th place

4ieee.org

652^nd place

515^th place

3harvard.edu

18^th place

17^th place

3eetimes.com

3,722^nd place

2,509^th place

2worldcat.org

5^th place

2highbeam.com

405^th place

256^th place

2handle.net

102^nd place

76^th place

2electroiq.com

low place

2berkeley.edu

580^th place

462^nd place

2intel.com

1,118^th place

825^th place

2pcmag.com

1,060^th place

700^th place

1itrs.net

low place

1datasheetspdf.com

low place

1alldatasheet.com

low place

1nxp.com

low place

8,784^th place

1computerhope.com

8,400^th place

6,430^th place

1psu.edu

207^th place

136^th place

1amd.com

2,816^th place

2,038^th place

1digitimes.com

low place

1marketwired.com

low place

6,052^nd place

1esilicon.com

low place

1samsung.com

2,554^th place

2,045^th place

1libero.it

3,224^th place

6,854^th place

1zdnet.co.uk

low place

1xbitlabs.com

low place

1dailytech.com

low place

8,724^th place

1arstechnica.com

388^th place

265^th place

1nature.com

234^th place

397^th place

1techradar.com

1,521^st place

944^th place

1purdue.edu

850^th place

625^th place

1arxiv.org

69^th place

59^th place

1unisantis-el.jp

low place

1semiengineering.com

low place

1extremetech.com

4,667^th place

3,322^nd place

1justia.com

696^th place

428^th place

1techxplore.com

low place

1allaboutcircuits.com

low place

1ietejournals.org

low place

allaboutcircuits.com

"Scaling Down: Intel Boasts RibbonFET and PowerVia as Next IC Design Solution - News". www.allaboutcircuits.com. Retrieved 2022-09-14.

alldatasheet.com

pdf1.alldatasheet.com

"3SK45 Datasheet - Alldatasheet.com" (PDF). Retrieved 2023-01-08.

amd.com

"AMD Newsroom". Amd.com. 2002-09-10. Archived from the original on 2010-05-13. Retrieved 2015-07-07.

anandtech.com

Shimpi, Anand Lal. "Intel Announces first 22nm 3D Tri-Gate Transistors, Shipping in 2H 2011". www.anandtech.com.
Smith, Ryan. "The AMD Radeon RX 480 Preview: Polaris Makes Its Mainstream Mark". Retrieved 2018-06-03.
Cutress, Dr Ian. "Where are my GAA-FETs? TSMC to Stay with FinFET for 3nm". www.anandtech.com.
Cutress, Ian. "Samsung Announces 3 nm GAA MBCFET PDK, Version 0.1". www.anandtech.com.
Cutress, Dr Ian. "Intel to use Nanowire/Nanoribbon Transistors in Volume 'in Five Years'". www.anandtech.com.

arstechnica.com

"Transistors go 3D as Intel re-invents the microchip". Ars Technica. 5 May 2011. Retrieved 7 May 2011.

arxiv.org

Gu, J. J.; Liu, Y. Q.; Wu, Y. Q.; Colby, R.; Gordon, R. G.; Ye, P. D. (December 2011). "First experimental demonstration of gate-all-around III–V MOSFETs by top-down approach" (PDF). 2011 International Electron Devices Meeting. pp. 33.2.1–33.2.4. arXiv:1112.3573. doi:10.1109/IEDM.2011.6131662. ISBN 978-1-4577-0505-2. S2CID 2116042. Retrieved 2015-05-10.

berkeley.edu

people.eecs.berkeley.edu

Tsu-Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". University of California, Berkeley. Symposium on VLSI Technology Short Course. Retrieved 9 July 2019.

www-device.eecs.berkeley.edu

"BSIMCMG Model". UC Berkeley. Archived from the original on 2012-07-21.

books.google.com

Colinge, J.P. (2008). FinFETs and Other Multi-Gate Transistors. Springer Science & Business Media. pp. 11 & 39. ISBN 978-0-387-71751-7.
Colinge, J.P. (2008). FinFETs and Other Multi-Gate Transistors. Springer Science & Business Media. p. 12. ISBN 978-0-387-71751-7.
Brozek, Tomasz (2017). Micro- and Nanoelectronics: Emerging Device Challenges and Solutions. CRC Press. pp. 116–7. ISBN 978-1-351-83134-5.
Claeys, C.; Murota, J.; Tao, M.; Iwai, H.; Deleonibus, S. (2015). ULSI Process Integration 9. The Electrochemical Society. p. 109. ISBN 978-1-60768-675-0.
Ishikawa, Fumitaro; Buyanova, Irina (2017). Novel Compound Semiconductor Nanowires: Materials, Devices, and Applications. CRC Press. p. 457. ISBN 978-1-315-34072-2.
Brozek, Tomasz (2017). Micro- and Nanoelectronics: Emerging Device Challenges and Solutions. CRC Press. p. 117. ISBN 978-1-351-83134-5.

computerhope.com

"What is Finfet?". Computer Hope. April 26, 2017. Retrieved 4 July 2019.

dailytech.com

"IDF 2011: Intel Looks to Take a Bite Out of ARM, AMD With 3D FinFET Tech". DailyTech. Archived from the original on 2014-03-10. Retrieved 2014-03-10.

datasheetspdf.com

"Motorola 3N201 Datasheet - Datasheetspdf.com". Datasheetpdf.com. Retrieved 2023-01-08.

digitimes.com

Josephine Lien; Steve Shen (31 March 2014). "TSMC likely to launch 16 nm FinFET+ process at year-end 2014, and "FinFET Turbo" later in 2015-16". DIGITIMES. Retrieved 2014-03-31.

doi.org

Wong, H-S.; Chan, K.; Taur, Y. (December 10, 1997). "Self-aligned (Top and bottom) double-gate MOSFET with a 25 nm thick silicon channel". International Electron Devices Meeting. IEDM Technical Digest. pp. 427–430. doi:10.1109/IEDM.1997.650416. ISBN 978-0-7803-4100-5. ISSN 0163-1918. S2CID 20947344.
Hisamoto, D.; Kaga, T.; Kawamoto, Y.; Takeda, E. (December 1989). "A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET". International Technical Digest on Electron Devices Meeting. pp. 833–836. doi:10.1109/IEDM.1989.74182. S2CID 114072236.
Hisamoto, Digh; Hu, Chenming; Bokor, J.; King, Tsu-Jae; Anderson, E.; et al. (December 2000). "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm". IEEE Transactions on Electron Devices. 47 (12): 2320–2325. Bibcode:2000ITED...47.2320H. CiteSeerX 10.1.1.211.204. doi:10.1109/16.887014.
Lee, Hyunjin; et al. (2006). "Sub-5nm All-Around Gate FinFET for Ultimate Scaling". 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers. pp. 58–59. doi:10.1109/VLSIT.2006.1705215. hdl:10203/698. ISBN 978-1-4244-0005-8. S2CID 26482358.
Rostami, M.; Mohanram, K. (2011). "Dual-Vth$ Independent-Gate FinFETs for Low Power Logic Circuits". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30 (3): 337–349. doi:10.1109/TCAD.2010.2097310. hdl:1911/72088. S2CID 2225579.
Hieda, K.; Horiguchi, Fumio; Watanabe, H.; Sunouchi, Kazumasa; Inoue, I.; Hamamoto, Takeshi (December 1987). "New effects of trench isolated transistor using side-wall gates". 1987 International Electron Devices Meeting. pp. 736–739. doi:10.1109/IEDM.1987.191536. S2CID 34381025.
Wong, Hon-Sum (December 1992). "Gate-current injection and surface impact ionization in MOSFET's with a gate induced virtual drain". International Technical Digest on Electron Devices Meeting. pp. 151–154. doi:10.1109/IEDM.1992.307330. ISBN 0-7803-0817-4. S2CID 114058374.
Cartwright J. (2011). "Intel enters the third dimension". Nature. doi:10.1038/news.2011.274. Retrieved 2015-05-10.
Singh, N.; Agarwal, A.; Bera, L. K.; Liow, T. Y.; Yang, R.; Rustagi, S. C.; Tung, C. H.; Kumar, R.; Lo, G. Q.; Balasubramanian, N.; Kwong, D. (2006). "High-Performance fully depleted Silicon Nanowire Gate-All-Around CMOS devices". IEEE Electron Device Letters. 27 (5): 383–386. Bibcode:2006IEDL...27..383S. doi:10.1109/LED.2006.873381. ISSN 0741-3106. S2CID 45576648.
Dastjerdy, E.; Ghayour, R.; Sarvari, H. (August 2012). "Simulation and analysis of the frequency performance of a new silicon nanowire MOSFET structure". Physica E. 45: 66–71. Bibcode:2012PhyE...45...66D. doi:10.1016/j.physe.2012.07.007.
Gu, J. J.; Liu, Y. Q.; Wu, Y. Q.; Colby, R.; Gordon, R. G.; Ye, P. D. (December 2011). "First experimental demonstration of gate-all-around III–V MOSFETs by top-down approach" (PDF). 2011 International Electron Devices Meeting. pp. 33.2.1–33.2.4. arXiv:1112.3573. doi:10.1109/IEDM.2011.6131662. ISBN 978-1-4577-0505-2. S2CID 2116042. Retrieved 2015-05-10.
Masuoka, Fujio; Takato, Hiroshi; Sunouchi, Kazumasa; Okabe, N.; Nitayama, Akihiro; Hieda, K.; Horiguchi, Fumio (December 1988). "High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs". Technical Digest., International Electron Devices Meeting. pp. 222–225. doi:10.1109/IEDM.1988.32796. S2CID 114148274.
Subramanian V (2010). "Multiple gate field-effect transistors for future CMOS technologies". IETE Technical Review. 27 (6): 446–454. doi:10.4103/0256-4602.72582 (inactive 2024-09-26). Archived from the original on March 23, 2012.{{cite journal}}: CS1 maint: DOI inactive as of September 2024 (link)
Subramanian (5 Dec 2005). "Device and circuit-level analog performance trade-offs: A comparative study of planar bulk FETs versus FinFETs". IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest. pp. 898–901. doi:10.1109/IEDM.2005.1609503. ISBN 0-7803-9268-X. S2CID 32683938.

eetimes.com

"Intel's FinFETs are less fin and more triangle". EE Times. Archived from the original on 2013-05-31. Retrieved 2014-03-10.
"Globalfoundries looks leapfrog fab rivals with new process". EE Times. Archived from the original on 2013-02-02. Retrieved 2014-03-10.
"TSMC taps ARM's V8 on road to 16 nm FinFET". EE Times. Archived from the original on 2012-11-01. Retrieved 2014-03-10.

electroiq.com

Intel to Present on 22-nm Tri-gate Technology at VLSI Symposium (ElectroIQ 2012) Archived April 15, 2012, at the Wayback Machine
"Below 22nm, spacers get unconventional: Interview with ASM". ELECTROIQ. Retrieved 2011-05-04.

esilicon.com

"High-performance, high-bandwidth IP platform for Samsung 14LPP process technology". 2017-03-22.

extremetech.com

"TSMC Plots an Aggressive Course for 3 nm Lithography and Beyond - ExtremeTech". www.extremetech.com.

handle.net

hdl.handle.net

Lee, Hyunjin; et al. (2006). "Sub-5nm All-Around Gate FinFET for Ultimate Scaling". 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers. pp. 58–59. doi:10.1109/VLSIT.2006.1705215. hdl:10203/698. ISBN 978-1-4244-0005-8. S2CID 26482358.
Rostami, M.; Mohanram, K. (2011). "Dual-Vth$ Independent-Gate FinFETs for Low Power Logic Circuits". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30 (3): 337–349. doi:10.1109/TCAD.2010.2097310. hdl:1911/72088. S2CID 2225579.

harvard.edu

ui.adsabs.harvard.edu

Hisamoto, Digh; Hu, Chenming; Bokor, J.; King, Tsu-Jae; Anderson, E.; et al. (December 2000). "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm". IEEE Transactions on Electron Devices. 47 (12): 2320–2325. Bibcode:2000ITED...47.2320H. CiteSeerX 10.1.1.211.204. doi:10.1109/16.887014.
Singh, N.; Agarwal, A.; Bera, L. K.; Liow, T. Y.; Yang, R.; Rustagi, S. C.; Tung, C. H.; Kumar, R.; Lo, G. Q.; Balasubramanian, N.; Kwong, D. (2006). "High-Performance fully depleted Silicon Nanowire Gate-All-Around CMOS devices". IEEE Electron Device Letters. 27 (5): 383–386. Bibcode:2006IEDL...27..383S. doi:10.1109/LED.2006.873381. ISSN 0741-3106. S2CID 45576648.
Dastjerdy, E.; Ghayour, R.; Sarvari, H. (August 2012). "Simulation and analysis of the frequency performance of a new silicon nanowire MOSFET structure". Physica E. 45: 66–71. Bibcode:2012PhyE...45...66D. doi:10.1016/j.physe.2012.07.007.

highbeam.com

"Still Room at the Bottom.(nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )", Nanoparticle News, 1 April 2006, archived from the original on 6 November 2012
"Still Room at the Bottom.(nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )", Nanoparticle News, 1 April 2006, archived from the original on 6 November 2012, retrieved 17 July 2019

ieee.org

spectrum.ieee.org

ieeexplore.ieee.org

Wilson, D.; Hayhurst, R.; Oblea, A.; Parke, S.; Hackler, D. "Flexfet: Independently-Double-Gated SOI Transistor With Variable Vt and 0.5V Operation Achieving Near Ideal Subthreshold Slope" SOI Conference, 2007 IEEE International [1]

ieee.org

"IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers. Archived from the original on September 9, 2018. Retrieved 4 July 2019.

ietejournals.org

tr.ietejournals.org

Subramanian V (2010). "Multiple gate field-effect transistors for future CMOS technologies". IETE Technical Review. 27 (6): 446–454. doi:10.4103/0256-4602.72582 (inactive 2024-09-26). Archived from the original on March 23, 2012.{{cite journal}}: CS1 maint: DOI inactive as of September 2024 (link)

intel.com

"Intel Silicon Technology Innovations". Intel.com. Archived from the original on September 3, 2011. Retrieved 2014-03-10.

newsroom.intel.com

"Intel Reinvents Transistors Using New 3-D Structure". Intel. Retrieved 5 April 2011.

itrs.net

Table39b Archived September 27, 2007, at the Wayback Machine

justia.com

trademarks.justia.com

"MBCFET Trademark of Samsung Electronics Co., Ltd. - Registration Number 5495359 - Serial Number 87447776 :: Justia Trademarks". trademarks.justia.com. Retrieved 2020-01-16.

libero.it

digidownload.libero.it

High Performance Non-Planar Tri-gate Transistor Architecture; Dr. Gerald Marcyk. Intel, 2002

marketwired.com

"AMD Demonstrates Revolutionary 14nm FinFET Polaris GPU Architecture". AMD. 4 January 2016. Retrieved 2016-01-04.

nature.com

Cartwright J. (2011). "Intel enters the third dimension". Nature. doi:10.1038/news.2011.274. Retrieved 2015-05-10.

nxp.com

"BF1217WR Datasheet" (PDF). Retrieved 2023-01-08.

pcmag.com

forwardthinking.pcmag.com

Miller, Michael J. "Intel Releases Ivy Bridge: First Processor with "Tri-Gate" Transistor". PC Magazine. Archived from the original on 2019-12-28. Retrieved 2012-04-23.

pcmag.com

Murray, Matthew (4 May 2011). "Intel's New Tri-Gate Ivy Bridge Transistors: 9 Things You Need to Know". PC Magazine. Retrieved 7 May 2011.

psu.edu

citeseerx.ist.psu.edu

Hisamoto, Digh; Hu, Chenming; Bokor, J.; King, Tsu-Jae; Anderson, E.; et al. (December 2000). "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm". IEEE Transactions on Electron Devices. 47 (12): 2320–2325. Bibcode:2000ITED...47.2320H. CiteSeerX 10.1.1.211.204. doi:10.1109/16.887014.

purdue.edu

engineering.purdue.edu

Gu, J. J.; Liu, Y. Q.; Wu, Y. Q.; Colby, R.; Gordon, R. G.; Ye, P. D. (December 2011). "First experimental demonstration of gate-all-around III–V MOSFETs by top-down approach" (PDF). 2011 International Electron Devices Meeting. pp. 33.2.1–33.2.4. arXiv:1112.3573. doi:10.1109/IEDM.2011.6131662. ISBN 978-1-4577-0505-2. S2CID 2116042. Retrieved 2015-05-10.

samsung.com

news.samsung.com

"Samsung and eSilicon Taped Out 14nm Network Processor with Rambus 28G SerDes Solution". 2017-03-22.

semanticscholar.org

api.semanticscholar.org

Wong, H-S.; Chan, K.; Taur, Y. (December 10, 1997). "Self-aligned (Top and bottom) double-gate MOSFET with a 25 nm thick silicon channel". International Electron Devices Meeting. IEDM Technical Digest. pp. 427–430. doi:10.1109/IEDM.1997.650416. ISBN 978-0-7803-4100-5. ISSN 0163-1918. S2CID 20947344.
Hisamoto, D.; Kaga, T.; Kawamoto, Y.; Takeda, E. (December 1989). "A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET". International Technical Digest on Electron Devices Meeting. pp. 833–836. doi:10.1109/IEDM.1989.74182. S2CID 114072236.
Lee, Hyunjin; et al. (2006). "Sub-5nm All-Around Gate FinFET for Ultimate Scaling". 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers. pp. 58–59. doi:10.1109/VLSIT.2006.1705215. hdl:10203/698. ISBN 978-1-4244-0005-8. S2CID 26482358.
Rostami, M.; Mohanram, K. (2011). "Dual-Vth$ Independent-Gate FinFETs for Low Power Logic Circuits". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30 (3): 337–349. doi:10.1109/TCAD.2010.2097310. hdl:1911/72088. S2CID 2225579.
Hieda, K.; Horiguchi, Fumio; Watanabe, H.; Sunouchi, Kazumasa; Inoue, I.; Hamamoto, Takeshi (December 1987). "New effects of trench isolated transistor using side-wall gates". 1987 International Electron Devices Meeting. pp. 736–739. doi:10.1109/IEDM.1987.191536. S2CID 34381025.
Wong, Hon-Sum (December 1992). "Gate-current injection and surface impact ionization in MOSFET's with a gate induced virtual drain". International Technical Digest on Electron Devices Meeting. pp. 151–154. doi:10.1109/IEDM.1992.307330. ISBN 0-7803-0817-4. S2CID 114058374.
Singh, N.; Agarwal, A.; Bera, L. K.; Liow, T. Y.; Yang, R.; Rustagi, S. C.; Tung, C. H.; Kumar, R.; Lo, G. Q.; Balasubramanian, N.; Kwong, D. (2006). "High-Performance fully depleted Silicon Nanowire Gate-All-Around CMOS devices". IEEE Electron Device Letters. 27 (5): 383–386. Bibcode:2006IEDL...27..383S. doi:10.1109/LED.2006.873381. ISSN 0741-3106. S2CID 45576648.
Gu, J. J.; Liu, Y. Q.; Wu, Y. Q.; Colby, R.; Gordon, R. G.; Ye, P. D. (December 2011). "First experimental demonstration of gate-all-around III–V MOSFETs by top-down approach" (PDF). 2011 International Electron Devices Meeting. pp. 33.2.1–33.2.4. arXiv:1112.3573. doi:10.1109/IEDM.2011.6131662. ISBN 978-1-4577-0505-2. S2CID 2116042. Retrieved 2015-05-10.
Masuoka, Fujio; Takato, Hiroshi; Sunouchi, Kazumasa; Okabe, N.; Nitayama, Akihiro; Hieda, K.; Horiguchi, Fumio (December 1988). "High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs". Technical Digest., International Electron Devices Meeting. pp. 222–225. doi:10.1109/IEDM.1988.32796. S2CID 114148274.
Subramanian (5 Dec 2005). "Device and circuit-level analog performance trade-offs: A comparative study of planar bulk FETs versus FinFETs". IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest. pp. 898–901. doi:10.1109/IEDM.2005.1609503. ISBN 0-7803-9268-X. S2CID 32683938.

semiengineering.com

LaPedus, Mark (25 January 2021). "New Transistor Structures At 3nm/2nm". Semiconductor Engineering. Retrieved 23 December 2022.

techradar.com

Dan Grabham (2011-05-06). "Intel's Tri-Gate transistors: everything you need to know". TechRadar. Retrieved 2022-01-21.

techxplore.com

"Samsung at foundry event talks about 3nm, MBCFET developments". techxplore.com.

unisantis-el.jp

"Company Profile". Unisantis Electronics. Archived from the original on 22 February 2007. Retrieved 17 July 2019.

web.archive.org

Table39b Archived September 27, 2007, at the Wayback Machine
"IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers. Archived from the original on September 9, 2018. Retrieved 4 July 2019.
"AMD Newsroom". Amd.com. 2002-09-10. Archived from the original on 2010-05-13. Retrieved 2015-07-07.
"Intel Silicon Technology Innovations". Intel.com. Archived from the original on September 3, 2011. Retrieved 2014-03-10.
"Still Room at the Bottom.(nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )", Nanoparticle News, 1 April 2006, archived from the original on 6 November 2012
"Intel's FinFETs are less fin and more triangle". EE Times. Archived from the original on 2013-05-31. Retrieved 2014-03-10.
"Globalfoundries looks leapfrog fab rivals with new process". EE Times. Archived from the original on 2013-02-02. Retrieved 2014-03-10.
"TSMC taps ARM's V8 on road to 16 nm FinFET". EE Times. Archived from the original on 2012-11-01. Retrieved 2014-03-10.
"AMD Details Its Triple-Gate Transistors". Xbitlabs.com. Archived from the original on 2014-03-10. Retrieved 2014-03-10.
"IDF 2011: Intel Looks to Take a Bite Out of ARM, AMD With 3D FinFET Tech". DailyTech. Archived from the original on 2014-03-10. Retrieved 2014-03-10.
Miller, Michael J. "Intel Releases Ivy Bridge: First Processor with "Tri-Gate" Transistor". PC Magazine. Archived from the original on 2019-12-28. Retrieved 2012-04-23.
Intel to Present on 22-nm Tri-gate Technology at VLSI Symposium (ElectroIQ 2012) Archived April 15, 2012, at the Wayback Machine
"Company Profile". Unisantis Electronics. Archived from the original on 22 February 2007. Retrieved 17 July 2019.
"Still Room at the Bottom.(nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )", Nanoparticle News, 1 April 2006, archived from the original on 6 November 2012, retrieved 17 July 2019
Subramanian V (2010). "Multiple gate field-effect transistors for future CMOS technologies". IETE Technical Review. 27 (6): 446–454. doi:10.4103/0256-4602.72582 (inactive 2024-09-26). Archived from the original on March 23, 2012.{{cite journal}}: CS1 maint: DOI inactive as of September 2024 (link)
"BSIMCMG Model". UC Berkeley. Archived from the original on 2012-07-21.

worldcat.org

search.worldcat.org

Wong, H-S.; Chan, K.; Taur, Y. (December 10, 1997). "Self-aligned (Top and bottom) double-gate MOSFET with a 25 nm thick silicon channel". International Electron Devices Meeting. IEDM Technical Digest. pp. 427–430. doi:10.1109/IEDM.1997.650416. ISBN 978-0-7803-4100-5. ISSN 0163-1918. S2CID 20947344.
Singh, N.; Agarwal, A.; Bera, L. K.; Liow, T. Y.; Yang, R.; Rustagi, S. C.; Tung, C. H.; Kumar, R.; Lo, G. Q.; Balasubramanian, N.; Kwong, D. (2006). "High-Performance fully depleted Silicon Nanowire Gate-All-Around CMOS devices". IEEE Electron Device Letters. 27 (5): 383–386. Bibcode:2006IEDL...27..383S. doi:10.1109/LED.2006.873381. ISSN 0741-3106. S2CID 45576648.

xbitlabs.com

"AMD Details Its Triple-Gate Transistors". Xbitlabs.com. Archived from the original on 2014-03-10. Retrieved 2014-03-10.

zdnet.co.uk

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