Out-of-order execution (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Out-of-order execution" in English language version.

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16doi.org

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14semanticscholar.org

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3researchgate.net

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2washington.edu

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2computerhistory.org

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1pcguide.com

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acm.org

dl.acm.org

Smith, James E.; Pleszkun, Andrew R. (June 1985). "Implementation of precise interrupts in pipelined processors". 12th ISCA.
(Expanded version published in May 1988 as Implementing Precise Interrupts in Pipelined Processors.)
Hwu, W.; Patt, Yale N. (1986). HPSm, a high performance restricted data flow architecture having minimal functionality. ACM. pp. 297–306. ISBN 978-0-8186-0719-6. Retrieved 2013-12-06. {{cite book}}: |work= ignored (help)
Ullah, Nasr; Holle, Matt (March 1993). "The MC88110 Implementation of Precise Exceptions in a Superscalar Architecture" (pdf). ACM Sigarch Computer Architecture News. 21. Motorola Inc.: 15–25. doi:10.1145/152479.152482. S2CID 7036627.
Smotherman, Mark; Chawla, Shuchi; Cox, Stan; Malloy, Brian (December 1993). "Instruction scheduling for the Motorola 88110". Proceedings of the 26th Annual International Symposium on Microarchitecture. pp. 257–262. doi:10.1109/MICRO.1993.282761. ISBN 0-8186-5280-2. S2CID 52806289.

anandtech.com

Anand Lal Shimpi (2013-05-06). "Intel's Silvermont Architecture Revealed: Getting Serious About Mobile". AnandTech.
"The Haswell Front End - Intel's Haswell Architecture Analyzed: Building a New PC and a New Intel".

apnews.com

Ziegler, Bart (March 7, 1991). "Unisys Unveils 'Top Gun' Mainframe Computers". AP News.

ardent-tool.com

Gwennap, Linley (28 March 1994). "NexGen Enters Market with 66-MHz Nx586" (PDF). Microprocessor Report. Archived from the original (PDF) on 2 December 2021.

bloomberg.com

"Unisys' New Mainframe Leaves Big Blue In The Dust". Bloomberg. March 25, 1991. The new A19 relies on "super-scalar" techniques from scientific computers to execute many instructions concurrently. The A19 can overlap as many as 140 operations, more than 10 times as many as conventional mainframes can.

books.google.com

Kukunas, Jim (2015). Power and Performance: Software Analysis and Optimization. Morgan Kaufman. p. 37. ISBN 9780128008140.

cjat.ir

Diefendorff, Keith; Allen, Michael (April 1992). "Organization of the Motorola 88110 superscalar RISC microprocessor" (PDF). IEEE Micro. 12 (2): 40–63. doi:10.1109/40.127582. S2CID 25668727. Archived from the original (PDF) on 2022-10-21.

clemson.edu

people.computing.clemson.edu

Smotherman, Mark. "Culler-7". Clemson University.

cmu.edu

course.ece.cmu.edu

Smith, James E. (July 1989). "Dynamic Instruction Scheduling and the Astronautics ZS-1" (PDF). Computer. 22 (7): 21–35. doi:10.1109/2.30730. S2CID 329170.
Smith, James E. (November 1984). "Decoupled Access/Execute Computer Architectures" (PDF). ACM Transactions on Computer Systems. 2 (4): 289–308. doi:10.1145/357401.357403. S2CID 13903321.
Le, Hung Q. et al. "IBM POWER6 microarchitecture" (PDF). IBM Journal of Research and Development. 51 (6). November 2007.

cs.cmu.edu

Gwennap, Linley (16 February 1995). "Intel's P6 Uses Decoupled Superscalar Design" (PDF). Microprocessor Report.

computerhistory.org

archive.computerhistory.org

Thornton (1970, p. 125-127) Thornton, James (1970). Design of a Computer: The Control Data 6600 (PDF). ISBN 9780673059536.
Thornton (1970, p. 48-50) Thornton, James (1970). Design of a Computer: The Control Data 6600 (PDF). ISBN 9780673059536.

doi.org

Tomasulo, Robert Marco (1967), "An Efficient Algorithm for Exploiting Multiple Arithmetic Units" (PDF), IBM Journal of Research and Development, 11 (1): 25–33, CiteSeerX 10.1.1.639.7540, doi:10.1147/rd.111.0025, S2CID 8445049, archived from the original (PDF) on 2018-06-12
Smith, James E. (July 1989). "Dynamic Instruction Scheduling and the Astronautics ZS-1" (PDF). Computer. 22 (7): 21–35. doi:10.1109/2.30730. S2CID 329170.
Smith, James E. (November 1984). "Decoupled Access/Execute Computer Architectures" (PDF). ACM Transactions on Computer Systems. 2 (4): 289–308. doi:10.1145/357401.357403. S2CID 13903321.
Grohoski, Gregory F. (January 1990). "Machine organization of the IBM RISC System/6000 processor" (PDF). IBM Journal of Research and Development. 34 (1): 37–58. doi:10.1147/rd.341.0037. Archived from the original (PDF) on January 9, 2005.
Smith, James E.; Sohi, Gurindar S. (December 1995). "The Microarchitecture of Superscalar Processors" (PDF). Proceedings of the IEEE. 83 (12): 1617. doi:10.1109/5.476078.
Liptay, John S. (July 1992). "Design of the IBM Enterprise System/9000 high-end processor" (PDF). IBM Journal of Research and Development. 36 (4): 713–731. doi:10.1147/rd.364.0713. Archived from the original (PDF) on January 17, 2005.
Ullah, Nasr; Holle, Matt (March 1993). "The MC88110 Implementation of Precise Exceptions in a Superscalar Architecture" (pdf). ACM Sigarch Computer Architecture News. 21. Motorola Inc.: 15–25. doi:10.1145/152479.152482. S2CID 7036627.
Diefendorff, Keith; Allen, Michael (April 1992). "Organization of the Motorola 88110 superscalar RISC microprocessor" (PDF). IEEE Micro. 12 (2): 40–63. doi:10.1109/40.127582. S2CID 25668727. Archived from the original (PDF) on 2022-10-21.
Smotherman, Mark; Chawla, Shuchi; Cox, Stan; Malloy, Brian (December 1993). "Instruction scheduling for the Motorola 88110". Proceedings of the 26th Annual International Symposium on Microarchitecture. pp. 257–262. doi:10.1109/MICRO.1993.282761. ISBN 0-8186-5280-2. S2CID 52806289.
Smith, James E.; Weiss, Shlomo (June 1994). "PowerPC 601 and Alpha 21064: A Tale of Two RISCs" (PDF). IEEE Computer. 27 (6): 46–58. doi:10.1109/2.294853. S2CID 1114841.
Sima, Dezsö (September–October 2000). "The design space of register renaming techniques". IEEE Micro. 20 (5): 70–83. CiteSeerX 10.1.1.387.6460. doi:10.1109/40.877952. S2CID 11012472.
Burgess, Brad; Ullah, Nasr; Van Overen, Peter; Ogden, Deene (June 1994). "The PowerPC 603 microprocessor". Communications of the ACM. 37 (6): 34–42. doi:10.1145/175208.175212. S2CID 34385975.
Song, S. Peter; Denman, Marvin; Chang, Joe (October 1994). "The PowerPC 604 RISC microprocessor" (PDF). IEEE Micro. 14 (5): 8. doi:10.1109/MM.1994.363071. S2CID 11603864.
Smith, J. E. (1984). "Decoupled access/execute computer architectures". ACM Transactions on Computer Systems. 2 (4): 289–308. CiteSeerX 10.1.1.127.4475. doi:10.1145/357401.357403. S2CID 13903321.
Kurian, L.; Hulina, P. T.; Coraor, L. D. (1994). "Memory latency effects in decoupled architectures" (PDF). IEEE Transactions on Computers. 43 (10): 1129–1139. doi:10.1109/12.324539. S2CID 6913858. Archived from the original (PDF) on 2018-06-12.
Dorojevets, M. N.; Oklobdzija, V. (1995). "Multithreaded decoupled architecture". International Journal of High Speed Computing. 7 (3): 465–480. doi:10.1142/S0129053395000257.

hotchips.org

old.hotchips.org

Diefendorff, Keith (August 1993). "PowerPC 601 Microprocessor" (PDF). Hot Chips.
"SPARC64+: HAL's Second Generation 64-bit SPARC Processor" (PDF). Hot Chips.

ibm.com

research.ibm.com

Grohoski, Gregory F. (January 1990). "Machine organization of the IBM RISC System/6000 processor" (PDF). IBM Journal of Research and Development. 34 (1): 37–58. doi:10.1147/rd.341.0037. Archived from the original (PDF) on January 9, 2005.
Liptay, John S. (July 1992). "Design of the IBM Enterprise System/9000 high-end processor" (PDF). IBM Journal of Research and Development. 36 (4): 713–731. doi:10.1147/rd.364.0713. Archived from the original (PDF) on January 17, 2005.

irisa.fr

"Le Sparc64". Research Institute of Computer Science and Random Systems (in French).

m88k.com

Smotherman, Mark (29 April 1994). "Motorola MC88110 Overview".

nxp.com

"PowerPC™ 601 RISC Microprocessor Technical Summary" (PDF). Retrieved 23 October 2022.
"PowerPC™ 603 RISC Microprocessor Technical Summary" (PDF). Retrieved 27 October 2022.

pcguide.com

"Out-of-order Execution". pcguide.com. Retrieved 2014-01-17. This flexibility improves performance since it allows execution with less 'waiting' time.

psu.edu

citeseerx.ist.psu.edu

Tomasulo, Robert Marco (1967), "An Efficient Algorithm for Exploiting Multiple Arithmetic Units" (PDF), IBM Journal of Research and Development, 11 (1): 25–33, CiteSeerX 10.1.1.639.7540, doi:10.1147/rd.111.0025, S2CID 8445049, archived from the original (PDF) on 2018-06-12
Moudgill, Mayan; Vassiliadis, Stamatis (January 1996). "On Precise Interrupts". p. 18. CiteSeerX 10.1.1.33.3304. Archived from the original (pdf) on 13 October 2022.
Sima, Dezsö (September–October 2000). "The design space of register renaming techniques". IEEE Micro. 20 (5): 70–83. CiteSeerX 10.1.1.387.6460. doi:10.1109/40.877952. S2CID 11012472.
Smith, J. E. (1984). "Decoupled access/execute computer architectures". ACM Transactions on Computer Systems. 2 (4): 289–308. CiteSeerX 10.1.1.127.4475. doi:10.1145/357401.357403. S2CID 13903321.

realworldtech.com

Kanter, David (2010-09-25). "Intel's Sandy Bridge Microarchitecture".

regis.org

"The Centennial Celebration". Regis High School. 2011-03-14. Retrieved 2022-06-25. The algorithm "allows sequential instructions that would normally be stalled due to certain dependencies to execute non-sequentially" (also known as out of order execution).

researchgate.net

Moore, Charles R.; Becker, Michael C. et al. "The PowerPC 601 microprocessor". IEEE Micro. 13 (5). September 1993.
Sima, Dezsö (September–October 2000). "The design space of register renaming techniques". IEEE Micro. 20 (5): 70–83. CiteSeerX 10.1.1.387.6460. doi:10.1109/40.877952. S2CID 11012472.
Dorojevets, M. N.; Oklobdzija, V. (1995). "Multithreaded decoupled architecture". International Journal of High Speed Computing. 7 (3): 465–480. doi:10.1142/S0129053395000257.

rtcgroup.com

Mallia, Lou. "Qualcomm High Performance Processor Core and Platform for Mobile Applications" (PDF). Archived from the original (PDF) on 29 October 2013.

semanticscholar.org

api.semanticscholar.org

Tomasulo, Robert Marco (1967), "An Efficient Algorithm for Exploiting Multiple Arithmetic Units" (PDF), IBM Journal of Research and Development, 11 (1): 25–33, CiteSeerX 10.1.1.639.7540, doi:10.1147/rd.111.0025, S2CID 8445049, archived from the original (PDF) on 2018-06-12
Smith, James E. (July 1989). "Dynamic Instruction Scheduling and the Astronautics ZS-1" (PDF). Computer. 22 (7): 21–35. doi:10.1109/2.30730. S2CID 329170.
Smith, James E. (November 1984). "Decoupled Access/Execute Computer Architectures" (PDF). ACM Transactions on Computer Systems. 2 (4): 289–308. doi:10.1145/357401.357403. S2CID 13903321.
Ullah, Nasr; Holle, Matt (March 1993). "The MC88110 Implementation of Precise Exceptions in a Superscalar Architecture" (pdf). ACM Sigarch Computer Architecture News. 21. Motorola Inc.: 15–25. doi:10.1145/152479.152482. S2CID 7036627.
Diefendorff, Keith; Allen, Michael (April 1992). "Organization of the Motorola 88110 superscalar RISC microprocessor" (PDF). IEEE Micro. 12 (2): 40–63. doi:10.1109/40.127582. S2CID 25668727. Archived from the original (PDF) on 2022-10-21.
Smotherman, Mark; Chawla, Shuchi; Cox, Stan; Malloy, Brian (December 1993). "Instruction scheduling for the Motorola 88110". Proceedings of the 26th Annual International Symposium on Microarchitecture. pp. 257–262. doi:10.1109/MICRO.1993.282761. ISBN 0-8186-5280-2. S2CID 52806289.
Smith, James E.; Weiss, Shlomo (June 1994). "PowerPC 601 and Alpha 21064: A Tale of Two RISCs" (PDF). IEEE Computer. 27 (6): 46–58. doi:10.1109/2.294853. S2CID 1114841.
Sima, Dezsö (September–October 2000). "The design space of register renaming techniques". IEEE Micro. 20 (5): 70–83. CiteSeerX 10.1.1.387.6460. doi:10.1109/40.877952. S2CID 11012472.
Burgess, Brad; Ullah, Nasr; Van Overen, Peter; Ogden, Deene (June 1994). "The PowerPC 603 microprocessor". Communications of the ACM. 37 (6): 34–42. doi:10.1145/175208.175212. S2CID 34385975.
Song, S. Peter; Denman, Marvin; Chang, Joe (October 1994). "The PowerPC 604 RISC microprocessor" (PDF). IEEE Micro. 14 (5): 8. doi:10.1109/MM.1994.363071. S2CID 11603864.
Smith, J. E. (1984). "Decoupled access/execute computer architectures". ACM Transactions on Computer Systems. 2 (4): 289–308. CiteSeerX 10.1.1.127.4475. doi:10.1145/357401.357403. S2CID 13903321.
Kurian, L.; Hulina, P. T.; Coraor, L. D. (1994). "Memory latency effects in decoupled architectures" (PDF). IEEE Transactions on Computers. 43 (10): 1129–1139. doi:10.1109/12.324539. S2CID 6913858. Archived from the original (PDF) on 2018-06-12.

pdfs.semanticscholar.org

Tomasulo, Robert Marco (1967), "An Efficient Algorithm for Exploiting Multiple Arithmetic Units" (PDF), IBM Journal of Research and Development, 11 (1): 25–33, CiteSeerX 10.1.1.639.7540, doi:10.1147/rd.111.0025, S2CID 8445049, archived from the original (PDF) on 2018-06-12
Kurian, L.; Hulina, P. T.; Coraor, L. D. (1994). "Memory latency effects in decoupled architectures" (PDF). IEEE Transactions on Computers. 43 (10): 1129–1139. doi:10.1109/12.324539. S2CID 6913858. Archived from the original (PDF) on 2018-06-12.

tuwien.ac.at

complang.tuwien.ac.at

Song, S. Peter; Denman, Marvin; Chang, Joe (October 1994). "The PowerPC 604 RISC microprocessor" (PDF). IEEE Micro. 14 (5): 8. doi:10.1109/MM.1994.363071. S2CID 11603864.

utoronto.ca

eecg.utoronto.ca

Smith, James E.; Weiss, Shlomo (June 1994). "PowerPC 601 and Alpha 21064: A Tale of Two RISCs" (PDF). IEEE Computer. 27 (6): 46–58. doi:10.1109/2.294853. S2CID 1114841.

virginia.edu

cs.virginia.edu

Smith, James E.; Pleszkun, Andrew R. (June 1985). "Implementation of precise interrupts in pipelined processors". 12th ISCA.
(Expanded version published in May 1988 as Implementing Precise Interrupts in Pipelined Processors.)

washington.edu

courses.cs.washington.edu

"Out-of-order execution" (PDF). cs.washington.edu. 2006. Retrieved 2014-01-17. don't wait for previous instructions to execute if this instruction does not depend on them
Smith, James E.; Sohi, Gurindar S. (December 1995). "The Microarchitecture of Superscalar Processors" (PDF). Proceedings of the IEEE. 83 (12): 1617. doi:10.1109/5.476078.

web.archive.org

Tomasulo, Robert Marco (1967), "An Efficient Algorithm for Exploiting Multiple Arithmetic Units" (PDF), IBM Journal of Research and Development, 11 (1): 25–33, CiteSeerX 10.1.1.639.7540, doi:10.1147/rd.111.0025, S2CID 8445049, archived from the original (PDF) on 2018-06-12
Moudgill, Mayan; Vassiliadis, Stamatis (January 1996). "On Precise Interrupts". p. 18. CiteSeerX 10.1.1.33.3304. Archived from the original (pdf) on 13 October 2022.
Grohoski, Gregory F. (January 1990). "Machine organization of the IBM RISC System/6000 processor" (PDF). IBM Journal of Research and Development. 34 (1): 37–58. doi:10.1147/rd.341.0037. Archived from the original (PDF) on January 9, 2005.
Liptay, John S. (July 1992). "Design of the IBM Enterprise System/9000 high-end processor" (PDF). IBM Journal of Research and Development. 36 (4): 713–731. doi:10.1147/rd.364.0713. Archived from the original (PDF) on January 17, 2005.
Diefendorff, Keith; Allen, Michael (April 1992). "Organization of the Motorola 88110 superscalar RISC microprocessor" (PDF). IEEE Micro. 12 (2): 40–63. doi:10.1109/40.127582. S2CID 25668727. Archived from the original (PDF) on 2022-10-21.
Gwennap, Linley (28 March 1994). "NexGen Enters Market with 66-MHz Nx586" (PDF). Microprocessor Report. Archived from the original (PDF) on 2 December 2021.
Mallia, Lou. "Qualcomm High Performance Processor Core and Platform for Mobile Applications" (PDF). Archived from the original (PDF) on 29 October 2013.
Kurian, L.; Hulina, P. T.; Coraor, L. D. (1994). "Memory latency effects in decoupled architectures" (PDF). IEEE Transactions on Computers. 43 (10): 1129–1139. doi:10.1109/12.324539. S2CID 6913858. Archived from the original (PDF) on 2018-06-12.

wisc.edu

pages.cs.wisc.edu

"Inside the Minor CPU model: Scoreboard". 2017-06-09. Retrieved 2023-01-09.