PSE-36 (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "PSE-36" in English language version.

refsWebsite
Global rank English rank
3rd place
3rd place
low place
low place
153rd place
151st place
5th place
5th place
194th place
643rd place
2,816th place
2,038th place
1,118th place
825th place
2,976th place
1,939th place
low place
low place
low place
low place
1st place
1st place
1,131st place
850th place

amd.com

developer.amd.com

  • AMD Corporation (September 2012). "Volume 2: System Programming" (PDF). AMD64 Architecture Programmer's Manual (3.22 ed.). AMD Corporation. pp. 25–26 and 125–126. Retrieved 2014-02-17.

authorsden.com

books.google.com

ibm.com

www-03.ibm.com

intel.com

  • "Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide, Part 1" (PDF). Intel. p. "4-5" and "4-11". If the PSE-36 mechanism is not supported, M is 32, and this row does not apply. If the PSE-36 mechanism is supported, M is the minimum of 40 and MAXPHYADDR (this row does not apply if MAXPHYADDR = 32). See Section 4.1.4 for how to determine MAXPHYADDR and whether the PSE-36 mechanism is supported. [...] CPUID.80000008H:EAX[7:0] reports the physical-address width supported by the processor. (For processors that do not support CPUID function 80000008H, the width is generally 36 if CPUID.01H:EDX.PAE [bit 6] = 1 and 32 otherwise.) This width is referred to as MAXPHYADDR. MAXPHYADDR is at most 52.

microsoft.com

msdn.microsoft.com

orpheuscomputing.com

  • "The Intel Extended Server Memory Architecture" (PDF). Intel Order Number: 243846-001. 1998. Retrieved 2014-03-01.

stechno.net

tomshardware.com

web.archive.org

wikiwix.com

archive.wikiwix.com

worldcat.org

search.worldcat.org