Parallel computing (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Parallel computing" in English language version.

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13doi.org

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acm.org

dl.acm.org

Gottlieb, Allan; Almasi, George S. (1989). Highly parallel computing. Redwood City, Calif.: Benjamin/Cummings. ISBN 978-0-8053-0177-9.
Amdahl, Gene M. (1967-04-18). "Validity of the single processor approach to achieving large scale computing capabilities". Proceedings of the April 18-20, 1967, spring joint computer conference on - AFIPS '67 (Spring). New York, NY, USA: Association for Computing Machinery. pp. 483–485. doi:10.1145/1465482.1465560. ISBN 978-1-4503-7895-6.
Bataille, M. (1972-04-01). "Something old: the Gamma 60 the computer that was ahead of its time". ACM SIGARCH Computer Architecture News. 1 (2): 10–15. doi:10.1145/641276.641278. ISSN 0163-5964. S2CID 34642285.

aconit.org

db.aconit.org

Tumlin, Smotherman (2023-08-14). "An Evaluation of the Design of the Gamma 60". ACONIT Computer History Museum. Department of Computer Science, Clemson University. Retrieved 2023-08-14.

archive.org

Hennessy, John L.; Patterson, David A.; Larus, James R. (1999). Computer organization and design: the hardware/software interface (2. ed., 3rd print. ed.). San Francisco: Kaufmann. ISBN 978-1-55860-428-5.
Minsky, Marvin (1986). The Society of Mind. New York: Simon & Schuster. pp. 17. ISBN 978-0-671-60740-1.
Minsky, Marvin (1986). The Society of Mind. New York: Simon & Schuster. pp. 29. ISBN 978-0-671-60740-1.
Blakeslee, Thomas (1996). Beyond the Conscious Mind. Unlocking the Secrets of the Self. Springer. pp. 6–7. ISBN 9780306452628.
Gazzaniga, Michael (1985). The Social Brain. Discovering the Networks of the Mind. Basic Books. pp. 77–79. ISBN 9780465078509.
Ornstein, Robert (1992). Evolution of Consciousness: The Origins of the Way We Think. pp. 2.

army.mil

arl.army.mil

Boggan, Sha'Kia and Daniel M. Pressel (August 2007). GPUs: An Emerging Platform for General-Purpose Computation Archived 2016-12-25 at the Wayback Machine (PDF). ARL-SR-154, U.S. Army Research Lab. Retrieved on November 7, 2007.

berkeley.edu

eecs.berkeley.edu

Asanovic, Krste et al. (December 18, 2006). "The Landscape of Parallel Computing Research: A View from Berkeley" (PDF). University of California, Berkeley. Technical Report No. UCB/EECS-2006-183. "Old [conventional wisdom]: Increasing clock frequency is the primary method of improving processor performance. New [conventional wisdom]: Increasing parallelism is the primary method of improving processor performance… Even representatives from Intel, a company generally associated with the 'higher clock-speed is better' position, warned that traditional approaches to maximizing performance through maximizing clock speed have been pushed to their limits."
Asanovic, Krste, et al. (December 18, 2006). "The Landscape of Parallel Computing Research: A View from Berkeley" (PDF). University of California, Berkeley. Technical Report No. UCB/EECS-2006-183. See table on pages 17–19.

books.google.com

R.W. Hockney, C.R. Jesshope. Parallel Computers 2: Architecture, Programming and Algorithms, Volume 2. 1988. p. 8 quote: "The earliest reference to parallelism in computer design is thought to be in General L. F. Menabrea's publication in… 1842, entitled Sketch of the Analytical Engine Invented by Charles Babbage".

computer.org

awards.computer.org

The Sidney Fernbach Award given to MPI inventor Bill Gropp Archived 2011-07-25 at the Wayback Machine refers to MPI as "the dominant HPC communications interface"

computerworld.com

Anthes, Gry (November 19, 2001). "The Power of Parallelism". Computerworld. Archived from the original on January 31, 2008. Retrieved 2008-01-08.

developforperformance.com

Krauss, Kirk J (2018). "Thread Safety for Performance". Develop for Performance. Archived from the original on 2018-05-13. Retrieved 2018-05-10.
Krauss, Kirk J (2018). "Threading for Performance". Develop for Performance. Archived from the original on 2018-05-13. Retrieved 2018-05-10.

doi.org

Bakos, Jason D. (2016-01-01), Bakos, Jason D. (ed.), "Chapter 2 - Multicore and data-level optimization: OpenMP and SIMD", Embedded Systems, Boston: Morgan Kaufmann, pp. 49–103, doi:10.1016/b978-0-12-800342-8.00002-x, ISBN 978-0-12-800342-8, retrieved 2024-11-18
Amdahl, Gene M. (1967-04-18). "Validity of the single processor approach to achieving large scale computing capabilities". Proceedings of the April 18-20, 1967, spring joint computer conference on - AFIPS '67 (Spring). New York, NY, USA: Association for Computing Machinery. pp. 483–485. doi:10.1145/1465482.1465560. ISBN 978-1-4503-7895-6.
Bernstein, Arthur J. (1 October 1966). "Analysis of Programs for Parallel Processing". IEEE Transactions on Electronic Computers. EC-15 (5): 757–763. doi:10.1109/PGEC.1966.264565.
Flynn, Michael J. (September 1972). "Some Computer Organizations and Their Effectiveness" (PDF). IEEE Transactions on Computers. C-21 (9): 948–960. doi:10.1109/TC.1972.5009071.
Kirkpatrick, Scott (2003). "COMPUTER SCIENCE: Rough Times Ahead". Science. 299 (5607): 668–669. doi:10.1126/science.1081623. PMID 12560537. S2CID 60622095.
Valueva, Maria; Valuev, Georgii; Semyonova, Nataliya; Lyakhov, Pavel; Chervyakov, Nikolay; Kaplun, Dmitry; Bogaevskiy, Danil (2019-06-20). "Construction of Residue Number System Using Hardware Efficient Diagonal Function". Electronics. 8 (6): 694. doi:10.3390/electronics8060694. ISSN 2079-9292. All simulated circuits were described in very high speed integrated circuit (VHSIC) hardware description language (VHDL). Hardware modeling was performed on Xilinx FPGA Artix 7 xc7a200tfbg484-2.
Gupta, Ankit; Suneja, Kriti (May 2020). "Hardware Design of Approximate Matrix Multiplier based on FPGA in Verilog". 2020 4th International Conference on Intelligent Computing and Control Systems (ICICCS). Madurai, India: IEEE. pp. 496–498. doi:10.1109/ICICCS48265.2020.9121004. ISBN 978-1-7281-4876-2. S2CID 219990653.
Maslennikov, Oleg (2002). "Systematic Generation of Executing Programs for Processor Elements in Parallel ASIC or FPGA-Based Systems and Their Transformation into VHDL-Descriptions of Processor Element Control Units". Lecture Notes in Computer Science, 2328/2002: p. 272.
Shimokawa, Y.; Fuwa, Y.; Aramaki, N. (18–21 November 1991). "A parallel ASIC VLSI neurocomputer for a large number of neurons and billion connections per second speed". [Proceedings] 1991 IEEE International Joint Conference on Neural Networks. Vol. 3. pp. 2162–2167. doi:10.1109/IJCNN.1991.170708. ISBN 978-0-7803-0227-3. S2CID 61094111.
Acken, Kevin P.; Irwin, Mary Jane; Owens, Robert M. (July 1998). "A Parallel ASIC Architecture for Efficient Fractal Image Coding". The Journal of VLSI Signal Processing. 19 (2): 97–113. Bibcode:1998JSPSy..19...97A. doi:10.1023/A:1008005616596. S2CID 2976028.
David R., Helman; David A., Bader; JaJa, Joseph (1998). "A Randomized Parallel Sorting Algorithm with an Experimental Study" (PDF). Journal of Parallel and Distributed Computing. 52: 1–23. doi:10.1006/jpdc.1998.1462. hdl:1903/835. Archived from the original (PDF) on 19 November 2012. Retrieved 26 October 2012.
Dobel, B., Hartig, H., & Engel, M. (2012) "Operating system support for redundant multithreading". Proceedings of the Tenth ACM International Conference on Embedded Software, 83–92. doi:10.1145/2380356.2380375
Bataille, M. (1972-04-01). "Something old: the Gamma 60 the computer that was ahead of its time". ACM SIGARCH Computer Architecture News. 1 (2): 10–15. doi:10.1145/641276.641278. ISSN 0163-5964. S2CID 34642285.

elsevier.com

linkinghub.elsevier.com

Bakos, Jason D. (2016-01-01), Bakos, Jason D. (ed.), "Chapter 2 - Multicore and data-level optimization: OpenMP and SIMD", Embedded Systems, Boston: Morgan Kaufmann, pp. 49–103, doi:10.1016/b978-0-12-800342-8.00002-x, ISBN 978-0-12-800342-8, retrieved 2024-11-18

embedded.com

Cecil, David (2015-11-03). "Synchronization internals – the semaphore". Embedded. AspenCore. Retrieved 2018-05-10.

feb-patrimoine.com

"Architecture Sketch of Bull Gamma 60 -- Mark Smotherman". www.feb-patrimoine.com. Retrieved 2023-08-14.

fourmilab.ch

Menabrea, L. F. (1842). Sketch of the Analytic Engine Invented by Charles Babbage. Bibliothèque Universelle de Genève. Retrieved on November 7, 2007. quote: "when a long series of identical computations is to be performed, such as those required for the formation of numerical tables, the machine can be brought into play so as to give several results at the same time, which will greatly abridge the whole amount of the processes."

future-fab.com

Kahng, Andrew B. (June 21, 2004) "Scoping the Problem of DFM in the Semiconductor Industry Archived 2008-01-31 at the Wayback Machine." University of California, San Diego. "Future design for manufacturing (DFM) technology must reduce design [non-recoverable expenditure] cost and directly address manufacturing [non-recoverable expenditures]—the cost of a mask set and probe card—which is well over $1 million at the 90 nm technology node and creates a significant damper on semiconductor-based innovation."

gatech.edu

cc.gatech.edu

David R., Helman; David A., Bader; JaJa, Joseph (1998). "A Randomized Parallel Sorting Algorithm with an Experimental Study" (PDF). Journal of Parallel and Distributed Computing. 52: 1–23. doi:10.1006/jpdc.1998.1462. hdl:1903/835. Archived from the original (PDF) on 19 November 2012. Retrieved 26 October 2012.

handle.net

hdl.handle.net

David R., Helman; David A., Bader; JaJa, Joseph (1998). "A Randomized Parallel Sorting Algorithm with an Experimental Study" (PDF). Journal of Parallel and Distributed Computing. 52: 1–23. doi:10.1006/jpdc.1998.1462. hdl:1903/835. Archived from the original (PDF) on 19 November 2012. Retrieved 26 October 2012.

harvard.edu

ui.adsabs.harvard.edu

Acken, Kevin P.; Irwin, Mary Jane; Owens, Robert M. (July 1998). "A Parallel ASIC Architecture for Efficient Fractal Image Coding". The Journal of VLSI Signal Processing. 19 (2): 97–113. Bibcode:1998JSPSy..19...97A. doi:10.1023/A:1008005616596. S2CID 2976028.

ieee.org

ieeexplore.ieee.org

Gupta, Ankit; Suneja, Kriti (May 2020). "Hardware Design of Approximate Matrix Multiplier based on FPGA in Verilog". 2020 4th International Conference on Intelligent Computing and Control Systems (ICICCS). Madurai, India: IEEE. pp. 496–498. doi:10.1109/ICICCS48265.2020.9121004. ISBN 978-1-7281-4876-2. S2CID 219990653.

illinois.edu

graphics.cs.illinois.edu

S.V. Adve et al. (November 2008). "Parallel Computing Research at Illinois: The UPCRC Agenda" Archived 2018-01-11 at the Wayback Machine (PDF). Parallel@Illinois, University of Illinois at Urbana-Champaign. "The main techniques for these performance benefits—increased clock frequency and smarter but increasingly complex architectures—are now hitting the so-called power wall. The computer industry has accepted that future performance increases must largely come from increasing the number of processors (or cores) on a die, rather than making a single core go faster."

informit.com

Tanenbaum, Andrew S. (2002-02-01). Introduction to Operating System Deadlocks. Pearson Education, Informit. Retrieved 2018-05-10. {{cite book}}: |website= ignored (help)

intel.com

software.intel.com

Kukanov, Alexey (2008-03-04). "Why a simple test can get parallel slowdown". Retrieved 2015-02-15.

llnl.gov

Barney, Blaise. "Introduction to Parallel Computing". Lawrence Livermore National Laboratory. Retrieved 2007-11-09.

microsoft.com

msdn.microsoft.com

"Processes and Threads". Microsoft Developer Network. Microsoft Corp. 2018. Retrieved 2018-05-10.

mit.edu

groups.csail.mit.edu

Samuel Larsen; Saman Amarasinghe. "Exploiting Superword Level Parallelism with Multimedia Instruction Sets" (PDF).

nersc.gov

"Interconnect" Archived 2015-01-28 at the Wayback Machine.

neuroclusterbrain.com

"Official Neurocluster Brain Model site". Retrieved July 22, 2017.

nih.gov

pubmed.ncbi.nlm.nih.gov

Kirkpatrick, Scott (2003). "COMPUTER SCIENCE: Rough Times Ahead". Science. 299 (5607): 668–669. doi:10.1126/science.1081623. PMID 12560537. S2CID 60622095.

nytimes.com

Flynn, Laurie J. (8 May 2004). "Intel Halts Development Of 2 New Microprocessors". New York Times. Retrieved 5 June 2012.

pcmag.com

Beowulf definition. Archived 2012-10-10 at the Wayback Machine PC Magazine. Retrieved on November 7, 2007.
MPP Definition. Archived 2013-05-11 at the Wayback Machine PC Magazine. Retrieved on November 7, 2007.

preshing.com

Preshing, Jeff (2012-06-08). "An Introduction to Lock-Free Programming". Preshing on Programming. Retrieved 2018-05-10.

semanticscholar.org

api.semanticscholar.org

Kirkpatrick, Scott (2003). "COMPUTER SCIENCE: Rough Times Ahead". Science. 299 (5607): 668–669. doi:10.1126/science.1081623. PMID 12560537. S2CID 60622095.
Gupta, Ankit; Suneja, Kriti (May 2020). "Hardware Design of Approximate Matrix Multiplier based on FPGA in Verilog". 2020 4th International Conference on Intelligent Computing and Control Systems (ICICCS). Madurai, India: IEEE. pp. 496–498. doi:10.1109/ICICCS48265.2020.9121004. ISBN 978-1-7281-4876-2. S2CID 219990653.
Shimokawa, Y.; Fuwa, Y.; Aramaki, N. (18–21 November 1991). "A parallel ASIC VLSI neurocomputer for a large number of neurons and billion connections per second speed". [Proceedings] 1991 IEEE International Joint Conference on Neural Networks. Vol. 3. pp. 2162–2167. doi:10.1109/IJCNN.1991.170708. ISBN 978-0-7803-0227-3. S2CID 61094111.
Acken, Kevin P.; Irwin, Mary Jane; Owens, Robert M. (July 1998). "A Parallel ASIC Architecture for Efficient Fractal Image Coding". The Journal of VLSI Signal Processing. 19 (2): 97–113. Bibcode:1998JSPSy..19...97A. doi:10.1023/A:1008005616596. S2CID 2976028.
Bataille, M. (1972-04-01). "Something old: the Gamma 60 the computer that was ahead of its time". ACM SIGARCH Computer Architecture News. 1 (2): 10–15. doi:10.1145/641276.641278. ISSN 0163-5964. S2CID 34642285.

stackoverflow.com

"What's the opposite of "embarrassingly parallel"?". StackOverflow. Retrieved 2018-05-10.
Schwartz, David (2011-08-15). "What is thread contention?". StackOverflow. Retrieved 2018-05-10.

top500.org

"List Statistics | TOP500 Supercomputer Sites". www.top500.org. Retrieved 2018-08-05.

utah.edu

cs.utah.edu

Flynn, Michael J. (September 1972). "Some Computer Organizations and Their Effectiveness" (PDF). IEEE Transactions on Computers. C-21 (9): 948–960. doi:10.1109/TC.1972.5009071.

utexas.edu

users.ece.utexas.edu

Patt, Yale (April 2004). "The Microprocessor Ten Years From Now: What Are The Challenges, How Do We Meet Them? Archived 2008-04-14 at the Wayback Machine (wmv). Distinguished Lecturer talk at Carnegie Mellon University. Retrieved on November 7, 2007.

vt.edu

ei.cs.vt.edu

Wilson, Gregory V. (1994). "The History of the Development of Parallel Computing". Virginia Tech/Norfolk State University, Interactive Learning with a Digital Library in Computer Science. Retrieved 2008-01-08.

web.archive.org

S.V. Adve et al. (November 2008). "Parallel Computing Research at Illinois: The UPCRC Agenda" Archived 2018-01-11 at the Wayback Machine (PDF). Parallel@Illinois, University of Illinois at Urbana-Champaign. "The main techniques for these performance benefits—increased clock frequency and smarter but increasingly complex architectures—are now hitting the so-called power wall. The computer industry has accepted that future performance increases must largely come from increasing the number of processors (or cores) on a die, rather than making a single core go faster."
Krauss, Kirk J (2018). "Thread Safety for Performance". Develop for Performance. Archived from the original on 2018-05-13. Retrieved 2018-05-10.
Krauss, Kirk J (2018). "Threading for Performance". Develop for Performance. Archived from the original on 2018-05-13. Retrieved 2018-05-10.
Patt, Yale (April 2004). "The Microprocessor Ten Years From Now: What Are The Challenges, How Do We Meet Them? Archived 2008-04-14 at the Wayback Machine (wmv). Distinguished Lecturer talk at Carnegie Mellon University. Retrieved on November 7, 2007.
Beowulf definition. Archived 2012-10-10 at the Wayback Machine PC Magazine. Retrieved on November 7, 2007.
"Interconnect" Archived 2015-01-28 at the Wayback Machine.
MPP Definition. Archived 2013-05-11 at the Wayback Machine PC Magazine. Retrieved on November 7, 2007.
Boggan, Sha'Kia and Daniel M. Pressel (August 2007). GPUs: An Emerging Platform for General-Purpose Computation Archived 2016-12-25 at the Wayback Machine (PDF). ARL-SR-154, U.S. Army Research Lab. Retrieved on November 7, 2007.
Kahng, Andrew B. (June 21, 2004) "Scoping the Problem of DFM in the Semiconductor Industry Archived 2008-01-31 at the Wayback Machine." University of California, San Diego. "Future design for manufacturing (DFM) technology must reduce design [non-recoverable expenditure] cost and directly address manufacturing [non-recoverable expenditures]—the cost of a mask set and probe card—which is well over $1 million at the 90 nm technology node and creates a significant damper on semiconductor-based innovation."
The Sidney Fernbach Award given to MPI inventor Bill Gropp Archived 2011-07-25 at the Wayback Machine refers to MPI as "the dominant HPC communications interface"
David R., Helman; David A., Bader; JaJa, Joseph (1998). "A Randomized Parallel Sorting Algorithm with an Experimental Study" (PDF). Journal of Parallel and Distributed Computing. 52: 1–23. doi:10.1006/jpdc.1998.1462. hdl:1903/835. Archived from the original (PDF) on 19 November 2012. Retrieved 26 October 2012.
Anthes, Gry (November 19, 2001). "The Power of Parallelism". Computerworld. Archived from the original on January 31, 2008. Retrieved 2008-01-08.

webopedia.com

What is clustering? Webopedia computer dictionary. Retrieved on November 7, 2007.

worldcat.org

search.worldcat.org

Valueva, Maria; Valuev, Georgii; Semyonova, Nataliya; Lyakhov, Pavel; Chervyakov, Nikolay; Kaplun, Dmitry; Bogaevskiy, Danil (2019-06-20). "Construction of Residue Number System Using Hardware Efficient Diagonal Function". Electronics. 8 (6): 694. doi:10.3390/electronics8060694. ISSN 2079-9292. All simulated circuits were described in very high speed integrated circuit (VHSIC) hardware description language (VHDL). Hardware modeling was performed on Xilinx FPGA Artix 7 xc7a200tfbg484-2.
Bataille, M. (1972-04-01). "Something old: the Gamma 60 the computer that was ahead of its time". ACM SIGARCH Computer Architecture News. 1 (2): 10–15. doi:10.1145/641276.641278. ISSN 0163-5964. S2CID 34642285.