Placement (electronic design automation) (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Placement (electronic design automation)" in English language version.

refsWebsite

Global rank English rank

11doi.org

2^nd place

6semanticscholar.org

11^th place

8^th place

3harvard.edu

18^th place

17^th place

3nih.gov

4^th place

3arxiv.org

69^th place

59^th place

1psu.edu

207^th place

136^th place

1espacenet.com

800^th place

676^th place

1ntu.edu.tw

2,798^th place

4,271^st place

1enterpriseai.news

low place

arxiv.org

Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan (2021). "A Graph Placement Methodology for Fast Chip Design". Nature. 594 (7862): 207–212. arXiv:2004.10746. Bibcode:2021Natur.594..207M. doi:10.1038/s41586-021-03544-w. PMID 34108699. S2CID 235395490.{{cite journal}}: CS1 maint: multiple names: authors list (link)
Cheng, Chung-Kuan, Andrew B. Kahng, Sayak Kundu, Yucheng Wang, and Zhiang Wang (Mar 2023). "Assessment of Reinforcement Learning for Macro Placement". Proceedings of the 2023 International Symposium on Physical Design. pp. 158–166. arXiv:2302.11014. doi:10.1145/3569052.3578926. ISBN 978-1-4503-9978-4.{{cite book}}: CS1 maint: multiple names: authors list (link)
Igor L. Markov (2023). "The False Dawn: Reevaluating Google's Reinforcement Learning for Chip Macro Placement". arXiv:2306.09633 [cs.LG].

doi.org

A. Kahng, J. Lienig, I. Markov, J. Hu: "VLSI Physical Design: From Graph Partitioning to Timing Closure", Springer (2022), doi:10.1007/978-90-481-9591-6, ISBN 978-3-030-96414-6, pp. 10-13.
A. Kahng, J. Lienig, I. Markov, J. Hu: "VLSI Physical Design: From Graph Partitioning to Timing Closure", Springer (2022), doi:10.1007/978-90-481-9591-6, ISBN 978-3-030-96414-6, pp. 14-15.
S. Kirkpatrick, C. D. G. Jr., and M. P. Vecchi (1983). "Optimization by Simulated Annealing". Science. 220 (4598): 671–680. Bibcode:1983Sci...220..671K. doi:10.1126/science.220.4598.671. PMID 17813860.{{cite journal}}: CS1 maint: multiple names: authors list (link)
Caldwell, A.E.; Kahng, A.B.; Markov, I.L. (June 2000). "Can recursive bisection alone produce routable placements?". Proceedings of the 37th Design Automation Conference. pp. 477–482. doi:10.1109/DAC.2000.855358.
Kleinhans, J.M.; Sigl, G.; Johannes, F.M.; Antreich, K.J. (March 1991). "GORDIAN: VLSI placement by quadratic programming and slicing optimization". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 10 (3): 356–365. doi:10.1109/43.67789. S2CID 15274014.
P. Spindler, U. Schlichtmann, and F. M. Johannes (2008). "Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model". IEEE Transactions on Computer-Aided Design. 27 (8): 1398–1411. doi:10.1109/TCAD.2008.925783. S2CID 16054185.{{cite journal}}: CS1 maint: multiple names: authors list (link)
Kim, M.-C.; Lee D.-J.; Markov I.L. (January 2011). "SimPL: An Effective Placement Algorithm". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31 (1): 50–60. CiteSeerX 10.1.1.187.1292. doi:10.1109/TCAD.2011.2170567. S2CID 47293399.
T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang (2008). "NTUPlace3: An Analytical Placer for Large-Scale Mixed-Size Designs with Preplaced Blocks and Density Constraint" (PDF). IEEE Transactions on Computer-Aided Design. 27 (7): 1228–1240. doi:10.1109/TCAD.2008.923063. S2CID 11912537.{{cite journal}}: CS1 maint: multiple names: authors list (link)
Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan (2021). "A Graph Placement Methodology for Fast Chip Design". Nature. 594 (7862): 207–212. arXiv:2004.10746. Bibcode:2021Natur.594..207M. doi:10.1038/s41586-021-03544-w. PMID 34108699. S2CID 235395490.{{cite journal}}: CS1 maint: multiple names: authors list (link)
Cheng, Chung-Kuan, Andrew B. Kahng, Sayak Kundu, Yucheng Wang, and Zhiang Wang (Mar 2023). "Assessment of Reinforcement Learning for Macro Placement". Proceedings of the 2023 International Symposium on Physical Design. pp. 158–166. arXiv:2302.11014. doi:10.1145/3569052.3578926. ISBN 978-1-4503-9978-4.{{cite book}}: CS1 maint: multiple names: authors list (link)
Kahng, Andrew B. (2021). "RETRACTED ARTICLE: AI system outperforms humans in designing floorplans for microchips". Nature. 594 (7862): 183–185. Bibcode:2021Natur.594..183K. doi:10.1038/d41586-021-01515-9. PMID 34108693. S2CID 235394411.

enterpriseai.news

Agam Shah (October 3, 2023). "Google's Controversial AI Chip Paper Under Scrutiny Again".

espacenet.com

worldwide.espacenet.com

USA 6301693, W. C. Naylor, R. Donelly, and L. Sha, "Non-Linear Optimization System and Method for Wire Length and Delay Optimization for an Automatic Electric Circuit Placer"

harvard.edu

ui.adsabs.harvard.edu

S. Kirkpatrick, C. D. G. Jr., and M. P. Vecchi (1983). "Optimization by Simulated Annealing". Science. 220 (4598): 671–680. Bibcode:1983Sci...220..671K. doi:10.1126/science.220.4598.671. PMID 17813860.{{cite journal}}: CS1 maint: multiple names: authors list (link)
Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan (2021). "A Graph Placement Methodology for Fast Chip Design". Nature. 594 (7862): 207–212. arXiv:2004.10746. Bibcode:2021Natur.594..207M. doi:10.1038/s41586-021-03544-w. PMID 34108699. S2CID 235395490.{{cite journal}}: CS1 maint: multiple names: authors list (link)
Kahng, Andrew B. (2021). "RETRACTED ARTICLE: AI system outperforms humans in designing floorplans for microchips". Nature. 594 (7862): 183–185. Bibcode:2021Natur.594..183K. doi:10.1038/d41586-021-01515-9. PMID 34108693. S2CID 235394411.

nih.gov

pubmed.ncbi.nlm.nih.gov

S. Kirkpatrick, C. D. G. Jr., and M. P. Vecchi (1983). "Optimization by Simulated Annealing". Science. 220 (4598): 671–680. Bibcode:1983Sci...220..671K. doi:10.1126/science.220.4598.671. PMID 17813860.{{cite journal}}: CS1 maint: multiple names: authors list (link)
Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan (2021). "A Graph Placement Methodology for Fast Chip Design". Nature. 594 (7862): 207–212. arXiv:2004.10746. Bibcode:2021Natur.594..207M. doi:10.1038/s41586-021-03544-w. PMID 34108699. S2CID 235395490.{{cite journal}}: CS1 maint: multiple names: authors list (link)
Kahng, Andrew B. (2021). "RETRACTED ARTICLE: AI system outperforms humans in designing floorplans for microchips". Nature. 594 (7862): 183–185. Bibcode:2021Natur.594..183K. doi:10.1038/d41586-021-01515-9. PMID 34108693. S2CID 235394411.

ntu.edu.tw

ntur.lib.ntu.edu.tw

T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang (2008). "NTUPlace3: An Analytical Placer for Large-Scale Mixed-Size Designs with Preplaced Blocks and Density Constraint" (PDF). IEEE Transactions on Computer-Aided Design. 27 (7): 1228–1240. doi:10.1109/TCAD.2008.923063. S2CID 11912537.{{cite journal}}: CS1 maint: multiple names: authors list (link)

psu.edu

citeseerx.ist.psu.edu

Kim, M.-C.; Lee D.-J.; Markov I.L. (January 2011). "SimPL: An Effective Placement Algorithm". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31 (1): 50–60. CiteSeerX 10.1.1.187.1292. doi:10.1109/TCAD.2011.2170567. S2CID 47293399.

semanticscholar.org

api.semanticscholar.org

Kleinhans, J.M.; Sigl, G.; Johannes, F.M.; Antreich, K.J. (March 1991). "GORDIAN: VLSI placement by quadratic programming and slicing optimization". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 10 (3): 356–365. doi:10.1109/43.67789. S2CID 15274014.
P. Spindler, U. Schlichtmann, and F. M. Johannes (2008). "Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model". IEEE Transactions on Computer-Aided Design. 27 (8): 1398–1411. doi:10.1109/TCAD.2008.925783. S2CID 16054185.{{cite journal}}: CS1 maint: multiple names: authors list (link)
Kim, M.-C.; Lee D.-J.; Markov I.L. (January 2011). "SimPL: An Effective Placement Algorithm". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31 (1): 50–60. CiteSeerX 10.1.1.187.1292. doi:10.1109/TCAD.2011.2170567. S2CID 47293399.
T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang (2008). "NTUPlace3: An Analytical Placer for Large-Scale Mixed-Size Designs with Preplaced Blocks and Density Constraint" (PDF). IEEE Transactions on Computer-Aided Design. 27 (7): 1228–1240. doi:10.1109/TCAD.2008.923063. S2CID 11912537.{{cite journal}}: CS1 maint: multiple names: authors list (link)
Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan (2021). "A Graph Placement Methodology for Fast Chip Design". Nature. 594 (7862): 207–212. arXiv:2004.10746. Bibcode:2021Natur.594..207M. doi:10.1038/s41586-021-03544-w. PMID 34108699. S2CID 235395490.{{cite journal}}: CS1 maint: multiple names: authors list (link)
Kahng, Andrew B. (2021). "RETRACTED ARTICLE: AI system outperforms humans in designing floorplans for microchips". Nature. 594 (7862): 183–185. Bibcode:2021Natur.594..183K. doi:10.1038/d41586-021-01515-9. PMID 34108693. S2CID 235394411.