Quadruple-precision floating-point format (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Quadruple-precision floating-point format" in English language version.

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7web.archive.org

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advanpix.com

Holoborodko, Pavel (2013-01-20). "Fast Quadruple Precision Computations in MATLAB". Retrieved 2015-06-22.

apple.com

developer.apple.com

Inside Macintosh – PowerPC Numerics. Archived October 9, 2012, at the Wayback Machine.

opensource.apple.com

128-bit long double support routines for Darwin.

arm.com

infocenter.arm.com

"Procedure Call Standard for the ARM 64-bit Architecture (AArch64)" (PDF). 2013-05-22. Archived from the original (PDF) on 2019-10-16. Retrieved 2019-09-22.

berkeley.edu

cs.berkeley.edu

Kahan, Wiliam (1 October 1987). "Lecture Notes on the Status of IEEE Standard 754 for Binary Floating-Point Arithmetic" (PDF).

boost.org

"Boost.Multiprecision – float128". Retrieved 2015-06-22.

cmu.edu

cs.cmu.edu

J. R. Shewchuk, Adaptive Precision Floating-Point Arithmetic and Fast Robust Geometric Predicates, Discrete & Computational Geometry 18: 305–363, 1997.

davidhbailey.com

Bailey, David H.; Borwein, Jonathan M. (July 6, 2009). "High-Precision Computation and Mathematical Physics" (PDF).

doi.org

Schwarz, E. M.; Krygowski, C. A. (September 1999). "The S/390 G5 floating-point unit". IBM Journal of Research and Development. 43 (5/6): 707–721. CiteSeerX 10.1.1.117.6711. doi:10.1147/rd.435.0707.
Padegs, A. (1968). "Structural aspects of the System/360 Model 85, III: Extensions to floating-point architecture". IBM Systems Journal. 7: 22–29. doi:10.1147/sj.71.0022.

github.com

"Carbon Language's main repository - Language design". GitHub. 2022-08-09. Retrieved 2022-09-22.
Cross, Travis. "Tracking Issue for f16 and f128 float types". GitHub. Retrieved 2024-07-05.
"DoubleFloats.jl". GitHub.
"doubledouble.py". GitHub.
RISC-V ISA Specification v. 20191213, Chapter 13, “Q” Standard Extension for Quad-Precision Floating-Point, page 79.
[1] Chapter 15, p. 95.

gnu.org

gcc.gnu.org

"GCC 4.6 Release Series - Changes, New Features, and Fixes". Retrieved 2010-02-06.
RS/6000 and PowerPC Options, Using the GNU Compiler Collection.
SPARC Options, Using the GNU Compiler Collection.
Additional Floating Types, Using the GNU Compiler Collection
"GCC 6 Release Series - Changes, New Features, and Fixes". Retrieved 2016-09-13.

ibm.com

pic.dhe.ibm.com

128-Bit Long Double Floating-Point Data Type.

ieee.org

grouper.ieee.org

"Implementor support for the binary interchange formats". IEEE. Archived from the original on 2017-10-27. Retrieved 2021-07-15.

inria.fr

arith22.gforge.inria.fr

Schwarz, Eric (June 22, 2015). "The IBM z13 SIMD Accelerators for Integer, String, and Floating-Point" (PDF). Retrieved July 13, 2015.

intel.com

software.intel.com

Intel Developer Site.
Intel C++ Forums (2007).

microsoft.com

msdn.microsoft.com

MSDN homepage, about Visual C++ compiler.

mit.edu

web.mit.edu

Yozo Hida, X. Li, and D. H. Bailey, Quad-Double Arithmetic: Algorithms, Implementation, and Application, Lawrence Berkeley National Laboratory Technical Report LBNL-46996 (2000). Also Y. Hida et al., Library for double-double and quad-double arithmetic (2007).

mrob.com

Robert Munafo. F107 and F161 High-Precision Floating-Point Data Types (2011).

open-std.org

"ISO/IEC TS 18661-3" (PDF). 2015-06-10. Retrieved 2019-09-22.

oracle.com

docs.oracle.com

The Math Libraries, Sun Studio 11 Numerical Computation Guide (2005).
"SPARC Behavior and Implementation". Numerical Computation Guide — Sun Studio 10. Sun Microsystems, Inc. 2004. Retrieved 2011-09-24. There are four situations, however, when the hardware will not successfully complete a floating-point instruction: ... The instruction is not implemented by the hardware (such as ... quad-precision instructions on any SPARC FPU).

psu.edu

citeseerx.ist.psu.edu

Yozo Hida, X. Li, and D. H. Bailey, Quad-Double Arithmetic: Algorithms, Implementation, and Application, Lawrence Berkeley National Laboratory Technical Report LBNL-46996 (2000). Also Y. Hida et al., Library for double-double and quad-double arithmetic (2007).
Schwarz, E. M.; Krygowski, C. A. (September 1999). "The S/390 G5 floating-point unit". IBM Journal of Research and Development. 43 (5/6): 707–721. CiteSeerX 10.1.1.117.6711. doi:10.1147/rd.435.0707.

sakura.ne.jp

sxauroratsubasa.sakura.ne.jp

Vector Engine AssemblyLanguage Reference Manual, Chapter4 Assembler Syntax page 23.
SX-Aurora TSUBASA Architecture Guide Revision 1.1, pp. 38, 60.

sourceware.org

sourceware.org Re: The state of glibc libm

sparc.org

The SPARC Architecture Manual: Version 8 (archived copy on web.archive.org) (PDF). SPARC International, Inc. 1992. Archived from the original (PDF) on 2005-02-04. Retrieved 2011-09-24. SPARC is an instruction set architecture (ISA) with 32-bit integer and 32-, 64-, and 128-bit IEEE Standard 754 floating-point as its principal data types.
Weaver, David L.; Germond, Tom, eds. (1994). The SPARC Architecture Manual: Version 9 (archived copy on web.archive.org) (PDF). SPARC International, Inc. Archived from the original (PDF) on 2012-01-18. Retrieved 2011-09-24. Floating-point: The architecture provides an IEEE 754-compatible floating-point instruction set, operating on a separate register file that provides 32 single-precision (32-bit), 32 double-precision (64-bit), 16 quad-precision (128-bit) registers, or a mixture thereof.

web.archive.org

"Intel Fortran Compiler Product Brief (archived copy on web.archive.org)" (PDF). Su. Archived from the original on October 25, 2008. Retrieved 2010-01-23.
i386 and x86-64 Options (archived copy on web.archive.org), Using the GNU Compiler Collection.
"Procedure Call Standard for the ARM 64-bit Architecture (AArch64)" (PDF). 2013-05-22. Archived from the original (PDF) on 2019-10-16. Retrieved 2019-09-22.
Inside Macintosh – PowerPC Numerics. Archived October 9, 2012, at the Wayback Machine.
"Implementor support for the binary interchange formats". IEEE. Archived from the original on 2017-10-27. Retrieved 2021-07-15.
The SPARC Architecture Manual: Version 8 (archived copy on web.archive.org) (PDF). SPARC International, Inc. 1992. Archived from the original (PDF) on 2005-02-04. Retrieved 2011-09-24. SPARC is an instruction set architecture (ISA) with 32-bit integer and 32-, 64-, and 128-bit IEEE Standard 754 floating-point as its principal data types.
Weaver, David L.; Germond, Tom, eds. (1994). The SPARC Architecture Manual: Version 9 (archived copy on web.archive.org) (PDF). SPARC International, Inc. Archived from the original (PDF) on 2012-01-18. Retrieved 2011-09-24. Floating-point: The architecture provides an IEEE 754-compatible floating-point instruction set, operating on a separate register file that provides 32 single-precision (32-bit), 32 double-precision (64-bit), 16 quad-precision (128-bit) registers, or a mixture thereof.

ziglang.org

"Floats". ziglang.org. Retrieved 7 January 2024.