Quasi-delay-insensitive circuit (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Quasi-delay-insensitive circuit" in English language version.

refsWebsite

Global rank English rank

22doi.org

2^nd place

16semanticscholar.org

11^th place

8^th place

7psu.edu

207^th place

136^th place

7caltech.edu

887^th place

714^th place

5cornell.edu

332^nd place

246^th place

4yale.edu

565^th place

460^th place

4worldcat.org

5^th place

2web.archive.org

1^st place

2handle.net

102^nd place

76^th place

2upc.edu

low place

1pdx.edu

8,132^nd place

5,327^th place

1technion.ac.il

low place

1utah.edu

2,446^th place

1,661^st place

1dtic.mil

833^rd place

567^th place

1researchgate.net

120^th place

125^th place

1bgu.ac.il

low place

bgu.ac.il

ee.bgu.ac.il

Nanya, T.; Ueno, Y.; Kagotani, H.; Kuwako, M.; Takamura, A. (Summer 1994). "TITAC: design of a quasi-delay-insensitive microprocessor" (PDF). IEEE Design and Test of Computers. 11 (2): 50–63. doi:10.1109/54.282445. ISSN 0740-7475. S2CID 9351043.

caltech.edu

authors.library.caltech.edu

Martin, Alain (1991). Synthesis of Asynchronous VLSI Circuits (PDF) (Report). California Institute of Technology.
Burns, Steven; Martin, Alain (1988). "Syntax-Directed Translation of Concurrent Programs into Self-Timed Circuits" (PDF). California Institute of Technology. {{cite journal}}: Cite journal requires |journal= (help)
Lines, Andrew (1998). "Pipelined Asynchronous Circuits" (PDF) (M.S.). California Institute of Technology. doi:10.7907/z92v2d4z. {{cite journal}}: Cite journal requires |journal= (help)
Martin, Alain J. (1990). "The Limitations to Delay-Insensitivity in Asynchronous Circuits" (PDF). Sixth MIT Conference on Advanced Research in VLSI. MIT Press.
Keller, S.; Katelman, M.; Martin, A. J. (May 2009). "A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits". 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (PDF). pp. 65–76. doi:10.1109/async.2009.27. ISBN 978-0-7695-3616-3. S2CID 6612621.

resolver.caltech.edu

Burns, Steven (1991). Performance Analysis and Optimization of Asynchronous Circuits (Ph.D.). California Institute of Technology.
Martin, Alain; Burns, Steven; Lee, Tak-Kwan (1989). "The design of an asynchronous microprocessor". ACM SIGARCH Computer Architecture News. 17 (4): 99–110. doi:10.1145/71317.1186643.

cornell.edu

vlsi.cornell.edu

Manohar, Rajit; Lee, Tak-Kwan; Martin, Alain (1999). "Projection: A synthesis technique for concurrent systems". Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (PDF). pp. 125–134. CiteSeerX 10.1.1.49.2264. doi:10.1109/ASYNC.1999.761528. ISBN 978-0-7695-0031-7. S2CID 11051137.
Manohar, Rajit; Martin, Alain J. (1998-06-15). "Slack elasticity in concurrent computing". Mathematics of Program Construction (PDF). Lecture Notes in Computer Science. Vol. 1422. Springer, Berlin, Heidelberg. pp. 272–285. CiteSeerX 10.1.1.396.2277. doi:10.1007/bfb0054295. ISBN 9783540645917.
Manohar, Rajit; Martin, Alain (1995). "Quasi-Delay-Insensitive Circuits are Turing-Complete" (PDF). California Institute of Technology. doi:10.7907/Z9H70CV1. {{cite journal}}: Cite journal requires |journal= (help)
Manohar, R.; Moses, Y. (May 2015). "Analyzing Isochronic Forks with Potential Causality". 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems (PDF). pp. 69–76. doi:10.1109/async.2015.19. ISBN 978-1-4799-8716-0. S2CID 10262182.
Longfield, Stephen; Nkounkou, Brittany; Manohar, Rajit; Tate, Ross (2015). "Preventing glitches and short circuits in high-level self-timed chip specifications". Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design and Implementation (PDF). PLDI '15. New York, NY, USA: ACM. pp. 270–279. doi:10.1145/2737924.2737967. ISBN 9781450334686. S2CID 6363535.

doi.org

Tse, Jonathan; Hill, Benjamin; Manohar, Rajit (May 2013). "A Bit of Analysis on Self-Timed Single-Bit On-Chip Links" (PDF). 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). pp. 124–133. CiteSeerX 10.1.1.649.294. doi:10.1109/ASYNC.2013.26. ISBN 978-1-4673-5956-6. S2CID 11196963.
Manohar, Rajit; Lee, Tak-Kwan; Martin, Alain (1999). "Projection: A synthesis technique for concurrent systems". Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (PDF). pp. 125–134. CiteSeerX 10.1.1.49.2264. doi:10.1109/ASYNC.1999.761528. ISBN 978-0-7695-0031-7. S2CID 11051137.
Manohar, Rajit; Martin, Alain J. (1998-06-15). "Slack elasticity in concurrent computing". Mathematics of Program Construction (PDF). Lecture Notes in Computer Science. Vol. 1422. Springer, Berlin, Heidelberg. pp. 272–285. CiteSeerX 10.1.1.396.2277. doi:10.1007/bfb0054295. ISBN 9783540645917.
Manohar, R. (2001). "An analysis of reshuffled handshaking expansions" (PDF). Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001. pp. 96–105. CiteSeerX 10.1.1.11.55. doi:10.1109/async.2001.914073. ISBN 978-0-7695-1034-7. S2CID 5156531. Archived from the original (PDF) on 2017-10-14.
Cortadella, J.; Kishinevsky, M.; Kondratyev, A.; Lavagno, L.; Yakovlev, A. (March 1996). "Complete state encoding based on the theory of regions". Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems (PDF). pp. 36–47. doi:10.1109/async.1996.494436. hdl:2117/129509. ISBN 978-0-8186-7298-9. S2CID 14297152.
Berkel, Kees van; Kessels, Joep; Roncken, Marly; Saeijs, Ronald; Schalij, Frits (1991). "The VLSI-programming language Tangram and its translation into handshake circuits" (PDF). Proceedings of the European Conference on Design Automation. IEEE Design Automation. pp. 384–389. doi:10.1109/EDAC.1991.206431. S2CID 34437785.
Lines, Andrew (1998). "Pipelined Asynchronous Circuits" (PDF) (M.S.). California Institute of Technology. doi:10.7907/z92v2d4z. {{cite journal}}: Cite journal requires |journal= (help)
Manohar, Rajit; Martin, Alain (1995). "Quasi-Delay-Insensitive Circuits are Turing-Complete" (PDF). California Institute of Technology. doi:10.7907/Z9H70CV1. {{cite journal}}: Cite journal requires |journal= (help)
Manohar, R.; Moses, Y. (May 2015). "Analyzing Isochronic Forks with Potential Causality". 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems (PDF). pp. 69–76. doi:10.1109/async.2015.19. ISBN 978-1-4799-8716-0. S2CID 10262182.
Keller, S.; Katelman, M.; Martin, A. J. (May 2009). "A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits". 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (PDF). pp. 65–76. doi:10.1109/async.2009.27. ISBN 978-0-7695-3616-3. S2CID 6612621.
LaFrieda, C.; Manohar, R. (May 2009). "Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits". 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (PDF). pp. 217–226. CiteSeerX 10.1.1.153.3557. doi:10.1109/async.2009.9. ISBN 978-0-7695-3616-3. S2CID 6282974.
Meng, T. H. Y.; Brodersen, R. W.; Messerschmitt, D. G. (November 1989). "Automatic synthesis of asynchronous circuits from high-level specifications". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 8 (11): 1185–1205. doi:10.1109/43.41504. ISSN 0278-0070.
Pastor, E.; Cortadella, J.; Kondratyev, A.; Roig, O. (November 1998). "Structural methods for the synthesis of speed-independent circuits" (PDF). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17 (11): 1108–1129. doi:10.1109/43.736185. hdl:2117/125785. ISSN 0278-0070.
Stevens, K. S.; Ginosar, R.; Rotem, S. (February 2003). "Relative timing" (PDF). IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 11 (1): 129–140. doi:10.1109/tvlsi.2002.801606. ISSN 1063-8210.
Manoranjan, J. V.; Stevens, K. S. (May 2016). "Qualifying Relative Timing Constraints for Asynchronous Circuits". 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) (PDF). pp. 91–98. doi:10.1109/async.2016.23. ISBN 978-1-4673-9007-1. S2CID 6239093.
Longfield, S. J.; Manohar, R. (May 2013). "Inverting Martin Synthesis for Verification". 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems (PDF). pp. 150–157. CiteSeerX 10.1.1.645.9939. doi:10.1109/async.2013.10. ISBN 978-1-4673-5956-6. S2CID 762078.
Longfield, Stephen; Nkounkou, Brittany; Manohar, Rajit; Tate, Ross (2015). "Preventing glitches and short circuits in high-level self-timed chip specifications". Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design and Implementation (PDF). PLDI '15. New York, NY, USA: ACM. pp. 270–279. doi:10.1145/2737924.2737967. ISBN 9781450334686. S2CID 6363535.
Karmazin, R.; Longfield, S.; Otero, C. T. O.; Manohar, R. (May 2015). "Timing Driven Placement for Quasi Delay-Insensitive Circuits". 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems (PDF). pp. 45–52. doi:10.1109/async.2015.16. ISBN 978-1-4799-8716-0. S2CID 10745504.
Martin, Alain; Burns, Steven; Lee, Tak-Kwan (1989). "The design of an asynchronous microprocessor". ACM SIGARCH Computer Architecture News. 17 (4): 99–110. doi:10.1145/71317.1186643.
Martin, Alain; Lines, Andrew; Manohar, Rajit; Nystrom, Mika; Penzes, Paul; Southworth, Robert; Cummings, Uri; Lee, Tak-Kwan (1997). "The design of an asynchronous MIPS R3000 microprocessor". Proceedings Seventeenth Conference on Advanced Research in VLSI. pp. 164–181. doi:10.1109/ARVLSI.1997.634853. ISBN 0-8186-7913-1.
Nanya, T.; Ueno, Y.; Kagotani, H.; Kuwako, M.; Takamura, A. (Summer 1994). "TITAC: design of a quasi-delay-insensitive microprocessor" (PDF). IEEE Design and Test of Computers. 11 (2): 50–63. doi:10.1109/54.282445. ISSN 0740-7475. S2CID 9351043.
Takamura, A.; Kuwako, M.; Imai, M.; Fujii, T.; Ozawa, M.; Fukasaku, I.; Ueno, Y.; Nanya, T. (October 1997). "TITAC-2: An asynchronous 32-bit microprocessor based on scalable-delay-insensitive model". Proceedings International Conference on Computer Design VLSI in Computers and Processors (PDF). pp. 288–294. CiteSeerX 10.1.1.53.7359. doi:10.1109/iccd.1997.628881. ISBN 978-0-8186-8206-3. S2CID 14119246. Archived from the original (PDF) on 2017-10-14.

dtic.mil

Lee, Tak-Kwan (1995). A General Approach to Performance Analysis and Optimization of Asynchronous Circuits (Ph.D.). Defense Technical Information Center.^{[dead link]}

handle.net

hdl.handle.net

Cortadella, J.; Kishinevsky, M.; Kondratyev, A.; Lavagno, L.; Yakovlev, A. (March 1996). "Complete state encoding based on the theory of regions". Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems (PDF). pp. 36–47. doi:10.1109/async.1996.494436. hdl:2117/129509. ISBN 978-0-8186-7298-9. S2CID 14297152.
Pastor, E.; Cortadella, J.; Kondratyev, A.; Roig, O. (November 1998). "Structural methods for the synthesis of speed-independent circuits" (PDF). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17 (11): 1108–1129. doi:10.1109/43.736185. hdl:2117/125785. ISSN 0278-0070.

pdx.edu

arc.cecs.pdx.edu

Berkel, Kees van; Kessels, Joep; Roncken, Marly; Saeijs, Ronald; Schalij, Frits (1991). "The VLSI-programming language Tangram and its translation into handshake circuits" (PDF). Proceedings of the European Conference on Design Automation. IEEE Design Automation. pp. 384–389. doi:10.1109/EDAC.1991.206431. S2CID 34437785.

psu.edu

citeseerx.ist.psu.edu

Tse, Jonathan; Hill, Benjamin; Manohar, Rajit (May 2013). "A Bit of Analysis on Self-Timed Single-Bit On-Chip Links" (PDF). 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). pp. 124–133. CiteSeerX 10.1.1.649.294. doi:10.1109/ASYNC.2013.26. ISBN 978-1-4673-5956-6. S2CID 11196963.
Manohar, Rajit; Lee, Tak-Kwan; Martin, Alain (1999). "Projection: A synthesis technique for concurrent systems". Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (PDF). pp. 125–134. CiteSeerX 10.1.1.49.2264. doi:10.1109/ASYNC.1999.761528. ISBN 978-0-7695-0031-7. S2CID 11051137.
Manohar, Rajit; Martin, Alain J. (1998-06-15). "Slack elasticity in concurrent computing". Mathematics of Program Construction (PDF). Lecture Notes in Computer Science. Vol. 1422. Springer, Berlin, Heidelberg. pp. 272–285. CiteSeerX 10.1.1.396.2277. doi:10.1007/bfb0054295. ISBN 9783540645917.
Manohar, R. (2001). "An analysis of reshuffled handshaking expansions" (PDF). Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001. pp. 96–105. CiteSeerX 10.1.1.11.55. doi:10.1109/async.2001.914073. ISBN 978-0-7695-1034-7. S2CID 5156531. Archived from the original (PDF) on 2017-10-14.
LaFrieda, C.; Manohar, R. (May 2009). "Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits". 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (PDF). pp. 217–226. CiteSeerX 10.1.1.153.3557. doi:10.1109/async.2009.9. ISBN 978-0-7695-3616-3. S2CID 6282974.
Longfield, S. J.; Manohar, R. (May 2013). "Inverting Martin Synthesis for Verification". 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems (PDF). pp. 150–157. CiteSeerX 10.1.1.645.9939. doi:10.1109/async.2013.10. ISBN 978-1-4673-5956-6. S2CID 762078.
Takamura, A.; Kuwako, M.; Imai, M.; Fujii, T.; Ozawa, M.; Fukasaku, I.; Ueno, Y.; Nanya, T. (October 1997). "TITAC-2: An asynchronous 32-bit microprocessor based on scalable-delay-insensitive model". Proceedings International Conference on Computer Design VLSI in Computers and Processors (PDF). pp. 288–294. CiteSeerX 10.1.1.53.7359. doi:10.1109/iccd.1997.628881. ISBN 978-0-8186-8206-3. S2CID 14119246. Archived from the original (PDF) on 2017-10-14.

researchgate.net

Martin, Alain; Lines, Andrew; Manohar, Rajit; Nystrom, Mika; Penzes, Paul; Southworth, Robert; Cummings, Uri; Lee, Tak-Kwan (1997). "The design of an asynchronous MIPS R3000 microprocessor". Proceedings Seventeenth Conference on Advanced Research in VLSI. pp. 164–181. doi:10.1109/ARVLSI.1997.634853. ISBN 0-8186-7913-1.

semanticscholar.org

api.semanticscholar.org

Tse, Jonathan; Hill, Benjamin; Manohar, Rajit (May 2013). "A Bit of Analysis on Self-Timed Single-Bit On-Chip Links" (PDF). 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). pp. 124–133. CiteSeerX 10.1.1.649.294. doi:10.1109/ASYNC.2013.26. ISBN 978-1-4673-5956-6. S2CID 11196963.
Manohar, Rajit; Lee, Tak-Kwan; Martin, Alain (1999). "Projection: A synthesis technique for concurrent systems". Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (PDF). pp. 125–134. CiteSeerX 10.1.1.49.2264. doi:10.1109/ASYNC.1999.761528. ISBN 978-0-7695-0031-7. S2CID 11051137.
Manohar, R. (2001). "An analysis of reshuffled handshaking expansions" (PDF). Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001. pp. 96–105. CiteSeerX 10.1.1.11.55. doi:10.1109/async.2001.914073. ISBN 978-0-7695-1034-7. S2CID 5156531. Archived from the original (PDF) on 2017-10-14.
Cortadella, J.; Kishinevsky, M.; Kondratyev, A.; Lavagno, L.; Yakovlev, A. (March 1996). "Complete state encoding based on the theory of regions". Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems (PDF). pp. 36–47. doi:10.1109/async.1996.494436. hdl:2117/129509. ISBN 978-0-8186-7298-9. S2CID 14297152.
Berkel, Kees van; Kessels, Joep; Roncken, Marly; Saeijs, Ronald; Schalij, Frits (1991). "The VLSI-programming language Tangram and its translation into handshake circuits" (PDF). Proceedings of the European Conference on Design Automation. IEEE Design Automation. pp. 384–389. doi:10.1109/EDAC.1991.206431. S2CID 34437785.
Manohar, R.; Moses, Y. (May 2015). "Analyzing Isochronic Forks with Potential Causality". 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems (PDF). pp. 69–76. doi:10.1109/async.2015.19. ISBN 978-1-4799-8716-0. S2CID 10262182.
Keller, S.; Katelman, M.; Martin, A. J. (May 2009). "A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits". 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (PDF). pp. 65–76. doi:10.1109/async.2009.27. ISBN 978-0-7695-3616-3. S2CID 6612621.
LaFrieda, C.; Manohar, R. (May 2009). "Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits". 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (PDF). pp. 217–226. CiteSeerX 10.1.1.153.3557. doi:10.1109/async.2009.9. ISBN 978-0-7695-3616-3. S2CID 6282974.
Manoranjan, J. V.; Stevens, K. S. (May 2016). "Qualifying Relative Timing Constraints for Asynchronous Circuits". 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) (PDF). pp. 91–98. doi:10.1109/async.2016.23. ISBN 978-1-4673-9007-1. S2CID 6239093.
Longfield, S. J.; Manohar, R. (May 2013). "Inverting Martin Synthesis for Verification". 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems (PDF). pp. 150–157. CiteSeerX 10.1.1.645.9939. doi:10.1109/async.2013.10. ISBN 978-1-4673-5956-6. S2CID 762078.
Longfield, Stephen; Nkounkou, Brittany; Manohar, Rajit; Tate, Ross (2015). "Preventing glitches and short circuits in high-level self-timed chip specifications". Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design and Implementation (PDF). PLDI '15. New York, NY, USA: ACM. pp. 270–279. doi:10.1145/2737924.2737967. ISBN 9781450334686. S2CID 6363535.
Karmazin, R.; Longfield, S.; Otero, C. T. O.; Manohar, R. (May 2015). "Timing Driven Placement for Quasi Delay-Insensitive Circuits". 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems (PDF). pp. 45–52. doi:10.1109/async.2015.16. ISBN 978-1-4799-8716-0. S2CID 10745504.
Nanya, T.; Ueno, Y.; Kagotani, H.; Kuwako, M.; Takamura, A. (Summer 1994). "TITAC: design of a quasi-delay-insensitive microprocessor" (PDF). IEEE Design and Test of Computers. 11 (2): 50–63. doi:10.1109/54.282445. ISSN 0740-7475. S2CID 9351043.
Takamura, A.; Kuwako, M.; Imai, M.; Fujii, T.; Ozawa, M.; Fukasaku, I.; Ueno, Y.; Nanya, T. (October 1997). "TITAC-2: An asynchronous 32-bit microprocessor based on scalable-delay-insensitive model". Proceedings International Conference on Computer Design VLSI in Computers and Processors (PDF). pp. 288–294. CiteSeerX 10.1.1.53.7359. doi:10.1109/iccd.1997.628881. ISBN 978-0-8186-8206-3. S2CID 14119246. Archived from the original (PDF) on 2017-10-14.

pdfs.semanticscholar.org

Manohar, R. (2001). "An analysis of reshuffled handshaking expansions" (PDF). Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001. pp. 96–105. CiteSeerX 10.1.1.11.55. doi:10.1109/async.2001.914073. ISBN 978-0-7695-1034-7. S2CID 5156531. Archived from the original (PDF) on 2017-10-14.
Takamura, A.; Kuwako, M.; Imai, M.; Fujii, T.; Ozawa, M.; Fukasaku, I.; Ueno, Y.; Nanya, T. (October 1997). "TITAC-2: An asynchronous 32-bit microprocessor based on scalable-delay-insensitive model". Proceedings International Conference on Computer Design VLSI in Computers and Processors (PDF). pp. 288–294. CiteSeerX 10.1.1.53.7359. doi:10.1109/iccd.1997.628881. ISBN 978-0-8186-8206-3. S2CID 14119246. Archived from the original (PDF) on 2017-10-14.

technion.ac.il

webee.technion.ac.il

Stevens, K. S.; Ginosar, R.; Rotem, S. (February 2003). "Relative timing" (PDF). IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 11 (1): 129–140. doi:10.1109/tvlsi.2002.801606. ISSN 1063-8210.

upc.edu

lsi.upc.edu

Cortadella, J.; Kishinevsky, M.; Kondratyev, A.; Lavagno, L.; Yakovlev, A. (March 1996). "Complete state encoding based on the theory of regions". Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems (PDF). pp. 36–47. doi:10.1109/async.1996.494436. hdl:2117/129509. ISBN 978-0-8186-7298-9. S2CID 14297152.

cs.upc.edu

Pastor, E.; Cortadella, J.; Kondratyev, A.; Roig, O. (November 1998). "Structural methods for the synthesis of speed-independent circuits" (PDF). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17 (11): 1108–1129. doi:10.1109/43.736185. hdl:2117/125785. ISSN 0278-0070.

utah.edu

ece.utah.edu

Manoranjan, J. V.; Stevens, K. S. (May 2016). "Qualifying Relative Timing Constraints for Asynchronous Circuits". 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) (PDF). pp. 91–98. doi:10.1109/async.2016.23. ISBN 978-1-4673-9007-1. S2CID 6239093.

web.archive.org

Manohar, R. (2001). "An analysis of reshuffled handshaking expansions" (PDF). Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001. pp. 96–105. CiteSeerX 10.1.1.11.55. doi:10.1109/async.2001.914073. ISBN 978-0-7695-1034-7. S2CID 5156531. Archived from the original (PDF) on 2017-10-14.
Takamura, A.; Kuwako, M.; Imai, M.; Fujii, T.; Ozawa, M.; Fukasaku, I.; Ueno, Y.; Nanya, T. (October 1997). "TITAC-2: An asynchronous 32-bit microprocessor based on scalable-delay-insensitive model". Proceedings International Conference on Computer Design VLSI in Computers and Processors (PDF). pp. 288–294. CiteSeerX 10.1.1.53.7359. doi:10.1109/iccd.1997.628881. ISBN 978-0-8186-8206-3. S2CID 14119246. Archived from the original (PDF) on 2017-10-14.

worldcat.org

search.worldcat.org

Meng, T. H. Y.; Brodersen, R. W.; Messerschmitt, D. G. (November 1989). "Automatic synthesis of asynchronous circuits from high-level specifications". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 8 (11): 1185–1205. doi:10.1109/43.41504. ISSN 0278-0070.
Pastor, E.; Cortadella, J.; Kondratyev, A.; Roig, O. (November 1998). "Structural methods for the synthesis of speed-independent circuits" (PDF). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17 (11): 1108–1129. doi:10.1109/43.736185. hdl:2117/125785. ISSN 0278-0070.
Stevens, K. S.; Ginosar, R.; Rotem, S. (February 2003). "Relative timing" (PDF). IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 11 (1): 129–140. doi:10.1109/tvlsi.2002.801606. ISSN 1063-8210.
Nanya, T.; Ueno, Y.; Kagotani, H.; Kuwako, M.; Takamura, A. (Summer 1994). "TITAC: design of a quasi-delay-insensitive microprocessor" (PDF). IEEE Design and Test of Computers. 11 (2): 50–63. doi:10.1109/54.282445. ISSN 0740-7475. S2CID 9351043.

yale.edu

csl.yale.edu

Tse, Jonathan; Hill, Benjamin; Manohar, Rajit (May 2013). "A Bit of Analysis on Self-Timed Single-Bit On-Chip Links" (PDF). 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). pp. 124–133. CiteSeerX 10.1.1.649.294. doi:10.1109/ASYNC.2013.26. ISBN 978-1-4673-5956-6. S2CID 11196963.
LaFrieda, C.; Manohar, R. (May 2009). "Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits". 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (PDF). pp. 217–226. CiteSeerX 10.1.1.153.3557. doi:10.1109/async.2009.9. ISBN 978-0-7695-3616-3. S2CID 6282974.
Longfield, S. J.; Manohar, R. (May 2013). "Inverting Martin Synthesis for Verification". 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems (PDF). pp. 150–157. CiteSeerX 10.1.1.645.9939. doi:10.1109/async.2013.10. ISBN 978-1-4673-5956-6. S2CID 762078.
Karmazin, R.; Longfield, S.; Otero, C. T. O.; Manohar, R. (May 2015). "Timing Driven Placement for Quasi Delay-Insensitive Circuits". 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems (PDF). pp. 45–52. doi:10.1109/async.2015.16. ISBN 978-1-4799-8716-0. S2CID 10745504.