Analysis of information sources in references of the Wikipedia article "Registered memory" in English language version.
This results in a reduction of maximum memory bandwidth for 2DPC configurations with UDIMM by some 5% in comparison to RDIMM..
But when you go to 2 DIMMs per memory channel, due to the high electrical loading on the address and control lines, the memory controller use something called a "2T" or "2N" timing for UDIMMs.
Consequently every command that normally takes a single clock cycle is stretched to two clock cycles to allow for settling time. Therefore, for two or more DIMMs per channel, RDIMMs will have lower latency and better bandwidth than UDIMMs.
