SONOS (English Wikipedia)

Chen, P. C. Y. (1977). "Threshold-alterable Si-gate MOS devices". IEEE Transactions on Electron Devices. 24 (5): 584–586. Bibcode:1977ITED...24..584C. doi:10.1109/T-ED.1977.18783. ISSN 0018-9383. S2CID 25586393.
Chen, S. C.; Chang, T. C.; Liu, P. T.; Wu, Y. C.; Lin, P. S.; Tseng, B. H.; Shy, J. H.; Sze, S. M.; Chang, C. Y.; Lien, C. H. (2007). "A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory". IEEE Electron Device Letters. 28 (9): 809–811. Bibcode:2007IEDL...28..809C. doi:10.1109/LED.2007.903885. ISSN 0741-3106. S2CID 40413991.
Lee, M. C.; Wong, H. Y. (2013). "Charge Loss Mechanisms of Nitride-Based Charge Trap Flash Memory Devices". IEEE Transactions on Electron Devices. 60 (10): 3256–3264. Bibcode:2013ITED...60.3256L. doi:10.1109/TED.2013.2279410. ISSN 0018-9383. S2CID 41506023.
Wang, S. Y.; Lue, H. T.; Hsu, T. H.; Du, P. Y.; Lai, S. C.; Hsiao, Y. H.; Hong, S. P.; Wu, M. T.; Hsu, F. H.; Lian, N. T.; Lu, C. P.; Hsieh, J. Y.; Yang, L. W.; Yang, T.; Chen, K. C.; Hsieh, K. Y.; Lu, C. Y. (2010). "A high-endurance (≫100K) BE-SONOS NAND flash with a robust nitrided tunnel oxide/Si interface". 2010 IEEE International Reliability Physics Symposium. pp. 951–955. doi:10.1109/IRPS.2010.5488698. ISBN 978-1-4244-5430-3. S2CID 23505564.
Arai, F.; Maruyama, T.; Shirota, R. (1998). "Extended data retention process technology for highly reliable flash EEPROMs of 10/Sup 6/ To 10/Sup 7/ W/E cycles". 1998 IEEE International Reliability Physics Symposium Proceedings 36th Annual (Cat No 98CH36173) RELPHY-98. pp. 378–382. doi:10.1109/RELPHY.1998.670672. ISBN 0-7803-4400-6. S2CID 110355820.
Frosch, C. J.; Derick, L (1957). "Surface Protection and Selective Masking during Diffusion in Silicon". Journal of the Electrochemical Society. 104 (9): 547. doi:10.1149/1.2428650.
KAHNG, D. (1961). "Silicon-Silicon Dioxide Surface Device". Technical Memorandum of Bell Laboratories: 583–596. doi:10.1142/9789814503464_0076. ISBN 978-981-02-0209-5. {{cite journal}}: ISBN / Date incompatibility (help)
Kahng, Dawon; Sze, Simon Min (July–August 1967). "A floating gate and its application to memory devices". The Bell System Technical Journal. 46 (6): 1288–1295. Bibcode:1967ITED...14Q.629K. doi:10.1002/j.1538-7305.1967.tb01738.x.
Wegener, H. A. R.; Lincoln, A. J.; Pao, H. C.; O'Connell, M. R.; Oleksiak, R. E.; Lawrence, H. (October 1967). The variable threshold transistor, a new electrically-alterable, non-destructive read-only storage device. 1967 International Electron Devices Meeting. Vol. 13. p. 70. doi:10.1109/IEDM.1967.187833.
Keshavan, B. V.; Lin, H. C. (October 1968). "MONOS memory element". 1968 International Electron Devices Meeting. Vol. 14. pp. 140–142. doi:10.1109/IEDM.1968.188066.
White, M.H.; Adams, D.A.; Bu, J. (2000). "On the go with SONOS". IEEE Circuits and Devices Magazine. 16 (4): 22–31. doi:10.1109/101.857747.
Johnson, W.; Perlegos, G.; Renninger, A.; Kuhn, G.; Ranganath, T. (1980). "A 16Kb electrically erasable nonvolatile memory". 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. Vol. XXIII. pp. 152–153. doi:10.1109/ISSCC.1980.1156030. S2CID 44313709.
Euzent, B.; Boruta, N.; Lee, J.; Jenq, C. (1981). "Reliability Aspects of a Floating Gate E2 PROM". 19th International Reliability Physics Symposium. pp. 11–16. doi:10.1109/IRPS.1981.362965. S2CID 41116025.
The Intel 2816 uses the FLOTOX structure, which has been discussed in detail in the literaturel. Basically, it utilizes an oxide of less than 200A thick between the floating polysilicon gate and the N+ region as shown in Figure 1.
Ohba, R.; Mitani, Y.; Sugiyama, N.; Fujita, S. (2006). "25 nm Planar Bulk SONOS-type Memory with Double Tunnel Junction". 2006 International Electron Devices Meeting. pp. 1–4. doi:10.1109/IEDM.2006.346945. ISBN 1-4244-0438-X. S2CID 5676069.
Sakamoto, W.; Yaegashi, T.; Okamura, T.; Toba, T.; Komiya, K.; Sakuma, K.; Matsunaga, Y.; Ishibashi, Y.; Nagashima, H.; Sugi, M.; Kawada, N.; Umemura, M.; Kondo, M.; Izumida, T.; Aoki, N.; Watanabe, T. (2009). "Reliability improvement in planar MONOS cell for 20nm-node multi-level NAND Flash memory and beyond". 2009 IEEE International Electron Devices Meeting (IEDM). pp. 1–4. doi:10.1109/IEDM.2009.5424211. ISBN 978-1-4244-5639-0. S2CID 29253924.
Kono, T.; Ito, T.; Tsuruda, T.; Nishiyama, T.; Nagasawa, T.; Ogawa, T.; Kawashima, Y.; Hidaka, H.; Yamauchi, T. (2013). "40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data". 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers. pp. 212–213. doi:10.1109/ISSCC.2013.6487704. ISBN 978-1-4673-4516-3. S2CID 29355030.
Fischer, T.; Nam, B. G.; Chang, L.; Kuroda, T.; Pertijs, M. A. P. (2013). "Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions". IEEE Journal of Solid-State Circuits. 49 (1): 4–8. doi:10.1109/JSSC.2013.2284658. ISSN 0018-9200.
Luo, L. Q.; Teo, Z. Q.; Kong, Y. J.; Deng, F. X.; Liu, J. Q.; Zhang, F.; Cai, X. S.; Tan, K. M.; Lim, K. Y.; Khoo, P.; Jung, S. M.; Siah, S. Y.; Shum, D.; Wang, C. M.; Xing, J. C.; Liu, G. Y.; Diao, Y.; Lin, G. M.; Tee, L.; Lemke, S. M.; Ghazavi, P.; Liu, X.; Do, N.; Pey, K. L.; Shubhakar, K. (May 2016). "Functionality Demonstration of a High-Density 2.5V Self-Aligned Split-Gate NVM Cell Embedded into 40nm CMOS Logic Process for Automotive Microcontrollers" (PDF). 2016 IEEE 8th International Memory Workshop (IMW). pp. 1–4. doi:10.1109/IMW.2016.7495271. ISBN 978-1-4673-8833-7. S2CID 36398631.
Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L. (31 October 2013). "Solution processed molecular floating gate for flexible flash memories". Scientific Reports. 3 (1). Macmillan Publishers Limited: 3093. Bibcode:2013NatSR...3E3093Z. doi:10.1038/srep03093. ISSN 2045-2322. PMC 3813938. PMID 24172758.
Luo, L. Q.; Teo, Z. Q.; Kong, Y. J.; Deng, F. X.; Liu, J. Q.; Zhang, F.; Cai, X. S.; Tan, K. M.; Lim, K. Y.; Khoo, P.; Jung, S. M.; Siah, S. Y.; Shum, D.; Wang, C. M.; Xing, J. C.; Liu, G. Y.; Diao, Y.; Lin, G. M.; Tee, L.; Lemke, S. M.; Ghazavi, P.; Liu, X.; Do, N.; Pey, K. L.; Shubhakar, K. (May 2016). "Functionality Demonstration of a High-Density 2.5V Self-Aligned Split-Gate NVM Cell Embedded into 40nm CMOS Logic Process for Automotive Microcontrollers" (PDF). 2016 IEEE 8th International Memory Workshop (IMW). pp. 1–4. doi:10.1109/IMW.2016.7495271. ISBN 978-1-4673-8833-7. S2CID 36398631.

economist.com (Global: 254^th place; English: 236^th place)

"Not just a flash in the pan". The Economist. March 11, 2006. Retrieved 10 September 2019.

eetimes.com (Global: 3,722^nd place; English: 2,509^th place)

Ramkumar, Krishnaswamy; Jin, Bo (29 Sep 2011). "Advantages of SONOS memory for embedded flash technology". EE Times.
LaPedus, Mark (19 Apr 2006). "UMC fabs Sonos memory chip". EE Times.
LaPedus, Mark (2007-12-12). "Toshiba puts new twist on SONOS | EE Times". EETimes.
Yoshida, Junko (2012-05-28). "Renesas, TSMC tout licensable MCU platform using 40-nm eFlash | EE Times". EETimes.

electroiq.com (Global: low place; English: low place)

Samsung unwraps 40nm "charge trap flash" device // ElectroIQ, 2006-09
Vogler, Debra (November 2007). "Spansion makes diversity play with SONOS-based MirrorBit technology | Solid State Technology". electroiq.com. Retrieved 23 March 2018.

fujitsu.com (Global: 7,354^th place; English: 9,689^th place)

fujitsu.com

"Mie Fujitsu and SST Announce Automotive Platform Development on 40nm Technology : MIE FUJITSU SEMICONDUCTOR LIMITED". www.fujitsu.com. 2017-08-07.
"Embedded Non-Volatile Memory Solutions : MIE FUJITSU SEMICONDUCTOR LIMITED". www.fujitsu.com. Fujitsu.

pr.fujitsu.com

"AMD, FUJITSU AND SAIFUN ANNOUNCE COLLABORATION - News Room - FUJITSU". pr.fujitsu.com.

globalfoundries.com (Global: low place; English: low place)

Luo, L. Q.; Teo, Z. Q.; Kong, Y. J.; Deng, F. X.; Liu, J. Q.; Zhang, F.; Cai, X. S.; Tan, K. M.; Lim, K. Y.; Khoo, P.; Jung, S. M.; Siah, S. Y.; Shum, D.; Wang, C. M.; Xing, J. C.; Liu, G. Y.; Diao, Y.; Lin, G. M.; Tee, L.; Lemke, S. M.; Ghazavi, P.; Liu, X.; Do, N.; Pey, K. L.; Shubhakar, K. (May 2016). "Functionality Demonstration of a High-Density 2.5V Self-Aligned Split-Gate NVM Cell Embedded into 40nm CMOS Logic Process for Automotive Microcontrollers" (PDF). 2016 IEEE 8th International Memory Workshop (IMW). pp. 1–4. doi:10.1109/IMW.2016.7495271. ISBN 978-1-4673-8833-7. S2CID 36398631.

harvard.edu (Global: 18^th place; English: 17^th place)

ui.adsabs.harvard.edu

Chen, P. C. Y. (1977). "Threshold-alterable Si-gate MOS devices". IEEE Transactions on Electron Devices. 24 (5): 584–586. Bibcode:1977ITED...24..584C. doi:10.1109/T-ED.1977.18783. ISSN 0018-9383. S2CID 25586393.
Chen, S. C.; Chang, T. C.; Liu, P. T.; Wu, Y. C.; Lin, P. S.; Tseng, B. H.; Shy, J. H.; Sze, S. M.; Chang, C. Y.; Lien, C. H. (2007). "A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory". IEEE Electron Device Letters. 28 (9): 809–811. Bibcode:2007IEDL...28..809C. doi:10.1109/LED.2007.903885. ISSN 0741-3106. S2CID 40413991.
Lee, M. C.; Wong, H. Y. (2013). "Charge Loss Mechanisms of Nitride-Based Charge Trap Flash Memory Devices". IEEE Transactions on Electron Devices. 60 (10): 3256–3264. Bibcode:2013ITED...60.3256L. doi:10.1109/TED.2013.2279410. ISSN 0018-9383. S2CID 41506023.
Kahng, Dawon; Sze, Simon Min (July–August 1967). "A floating gate and its application to memory devices". The Bell System Technical Journal. 46 (6): 1288–1295. Bibcode:1967ITED...14Q.629K. doi:10.1002/j.1538-7305.1967.tb01738.x.
Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L. (31 October 2013). "Solution processed molecular floating gate for flexible flash memories". Scientific Reports. 3 (1). Macmillan Publishers Limited: 3093. Bibcode:2013NatSR...3E3093Z. doi:10.1038/srep03093. ISSN 2045-2322. PMC 3813938. PMID 24172758.

iop.org (Global: 1,725^th place; English: 1,828^th place)

iopscience.iop.org

Frosch, C. J.; Derick, L (1957). "Surface Protection and Selective Masking during Diffusion in Silicon". Journal of the Electrochemical Society. 104 (9): 547. doi:10.1149/1.2428650.

nih.gov (Global: 4^th place; English: 4^th place)

ncbi.nlm.nih.gov

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L. (31 October 2013). "Solution processed molecular floating gate for flexible flash memories". Scientific Reports. 3 (1). Macmillan Publishers Limited: 3093. Bibcode:2013NatSR...3E3093Z. doi:10.1038/srep03093. ISSN 2045-2322. PMC 3813938. PMID 24172758.

pubmed.ncbi.nlm.nih.gov

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L. (31 October 2013). "Solution processed molecular floating gate for flexible flash memories". Scientific Reports. 3 (1). Macmillan Publishers Limited: 3093. Bibcode:2013NatSR...3E3093Z. doi:10.1038/srep03093. ISSN 2045-2322. PMC 3813938. PMID 24172758.

patents.google.com (Global: 1,182^nd place; English: 725^th place)

TRUDEL, L; DHAM, V (1980-09-11). "Application WO1981000790: Silicon gate non-volatile memory device". Google Patents. NCR Corporation. The initialization procedure (steps 1, 4 and 7), i.e. obtaining the initial written and erased state threshold voltages, involved applying +25 volts for three seconds and -25 volts for three seconds, respectively, at room temperature to the gates of the memory FETs. Source, drain and substrate were all tied to ground during this initialization.
TRUDEL, MURRAY L; LOCKWOOD, GEORGE C; EVANS, EVANS G (1980-10-01). "Patent US4353083: Low voltage nonvolatile memory device". Google Patents. NCR Corporation.

prnewswire.com (Global: 406^th place; English: 258^th place)

"HLMC and Cypress Announce Initial Production Milestone of Embedded Flash Using 55-Nanometer Low Power Process Technology with SONOS Flash". PRNewswire. 12 Apr 2017.

psu.edu (Global: 207^th place; English: 136^th place)

citeseerx.ist.psu.edu

Remond, I.; Akil, N. (May 2006). "Modeling of transient programming and erasing of SONOS non-volatile memories". Technical Note PR-TN 2006/00368. Koninklijke Philips Electronics N.V. CiteSeerX 10.1.1.72.314.

researchgate.net (Global: 120^th place; English: 125^th place)

Chen, S. C.; Chang, T. C.; Liu, P. T.; Wu, Y. C.; Lin, P. S.; Tseng, B. H.; Shy, J. H.; Sze, S. M.; Chang, C. Y.; Lien, C. H. (2007). "A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory". IEEE Electron Device Letters. 28 (9): 809–811. Bibcode:2007IEDL...28..809C. doi:10.1109/LED.2007.903885. ISSN 0741-3106. S2CID 40413991.
Lee, M. C.; Wong, H. Y. (2013). "Charge Loss Mechanisms of Nitride-Based Charge Trap Flash Memory Devices". IEEE Transactions on Electron Devices. 60 (10): 3256–3264. Bibcode:2013ITED...60.3256L. doi:10.1109/TED.2013.2279410. ISSN 0018-9383. S2CID 41506023.
Luo, L. Q.; Teo, Z. Q.; Kong, Y. J.; Deng, F. X.; Liu, J. Q.; Zhang, F.; Cai, X. S.; Tan, K. M.; Lim, K. Y.; Khoo, P.; Jung, S. M.; Siah, S. Y.; Shum, D.; Wang, C. M.; Xing, J. C.; Liu, G. Y.; Diao, Y.; Lin, G. M.; Tee, L.; Lemke, S. M.; Ghazavi, P.; Liu, X.; Do, N.; Pey, K. L.; Shubhakar, K. (May 2016). "Functionality Demonstration of a High-Density 2.5V Self-Aligned Split-Gate NVM Cell Embedded into 40nm CMOS Logic Process for Automotive Microcontrollers" (PDF). 2016 IEEE 8th International Memory Workshop (IMW). pp. 1–4. doi:10.1109/IMW.2016.7495271. ISBN 978-1-4673-8833-7. S2CID 36398631.

semanticscholar.org (Global: 11^th place; English: 8^th place)

api.semanticscholar.org

Chen, P. C. Y. (1977). "Threshold-alterable Si-gate MOS devices". IEEE Transactions on Electron Devices. 24 (5): 584–586. Bibcode:1977ITED...24..584C. doi:10.1109/T-ED.1977.18783. ISSN 0018-9383. S2CID 25586393.
Chen, S. C.; Chang, T. C.; Liu, P. T.; Wu, Y. C.; Lin, P. S.; Tseng, B. H.; Shy, J. H.; Sze, S. M.; Chang, C. Y.; Lien, C. H. (2007). "A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory". IEEE Electron Device Letters. 28 (9): 809–811. Bibcode:2007IEDL...28..809C. doi:10.1109/LED.2007.903885. ISSN 0741-3106. S2CID 40413991.
Lee, M. C.; Wong, H. Y. (2013). "Charge Loss Mechanisms of Nitride-Based Charge Trap Flash Memory Devices". IEEE Transactions on Electron Devices. 60 (10): 3256–3264. Bibcode:2013ITED...60.3256L. doi:10.1109/TED.2013.2279410. ISSN 0018-9383. S2CID 41506023.
Wang, S. Y.; Lue, H. T.; Hsu, T. H.; Du, P. Y.; Lai, S. C.; Hsiao, Y. H.; Hong, S. P.; Wu, M. T.; Hsu, F. H.; Lian, N. T.; Lu, C. P.; Hsieh, J. Y.; Yang, L. W.; Yang, T.; Chen, K. C.; Hsieh, K. Y.; Lu, C. Y. (2010). "A high-endurance (≫100K) BE-SONOS NAND flash with a robust nitrided tunnel oxide/Si interface". 2010 IEEE International Reliability Physics Symposium. pp. 951–955. doi:10.1109/IRPS.2010.5488698. ISBN 978-1-4244-5430-3. S2CID 23505564.
Arai, F.; Maruyama, T.; Shirota, R. (1998). "Extended data retention process technology for highly reliable flash EEPROMs of 10/Sup 6/ To 10/Sup 7/ W/E cycles". 1998 IEEE International Reliability Physics Symposium Proceedings 36th Annual (Cat No 98CH36173) RELPHY-98. pp. 378–382. doi:10.1109/RELPHY.1998.670672. ISBN 0-7803-4400-6. S2CID 110355820.
Johnson, W.; Perlegos, G.; Renninger, A.; Kuhn, G.; Ranganath, T. (1980). "A 16Kb electrically erasable nonvolatile memory". 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. Vol. XXIII. pp. 152–153. doi:10.1109/ISSCC.1980.1156030. S2CID 44313709.
Euzent, B.; Boruta, N.; Lee, J.; Jenq, C. (1981). "Reliability Aspects of a Floating Gate E2 PROM". 19th International Reliability Physics Symposium. pp. 11–16. doi:10.1109/IRPS.1981.362965. S2CID 41116025.
The Intel 2816 uses the FLOTOX structure, which has been discussed in detail in the literaturel. Basically, it utilizes an oxide of less than 200A thick between the floating polysilicon gate and the N+ region as shown in Figure 1.
Ohba, R.; Mitani, Y.; Sugiyama, N.; Fujita, S. (2006). "25 nm Planar Bulk SONOS-type Memory with Double Tunnel Junction". 2006 International Electron Devices Meeting. pp. 1–4. doi:10.1109/IEDM.2006.346945. ISBN 1-4244-0438-X. S2CID 5676069.
Sakamoto, W.; Yaegashi, T.; Okamura, T.; Toba, T.; Komiya, K.; Sakuma, K.; Matsunaga, Y.; Ishibashi, Y.; Nagashima, H.; Sugi, M.; Kawada, N.; Umemura, M.; Kondo, M.; Izumida, T.; Aoki, N.; Watanabe, T. (2009). "Reliability improvement in planar MONOS cell for 20nm-node multi-level NAND Flash memory and beyond". 2009 IEEE International Electron Devices Meeting (IEDM). pp. 1–4. doi:10.1109/IEDM.2009.5424211. ISBN 978-1-4244-5639-0. S2CID 29253924.
Kono, T.; Ito, T.; Tsuruda, T.; Nishiyama, T.; Nagasawa, T.; Ogawa, T.; Kawashima, Y.; Hidaka, H.; Yamauchi, T. (2013). "40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data". 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers. pp. 212–213. doi:10.1109/ISSCC.2013.6487704. ISBN 978-1-4673-4516-3. S2CID 29355030.
Luo, L. Q.; Teo, Z. Q.; Kong, Y. J.; Deng, F. X.; Liu, J. Q.; Zhang, F.; Cai, X. S.; Tan, K. M.; Lim, K. Y.; Khoo, P.; Jung, S. M.; Siah, S. Y.; Shum, D.; Wang, C. M.; Xing, J. C.; Liu, G. Y.; Diao, Y.; Lin, G. M.; Tee, L.; Lemke, S. M.; Ghazavi, P.; Liu, X.; Do, N.; Pey, K. L.; Shubhakar, K. (May 2016). "Functionality Demonstration of a High-Density 2.5V Self-Aligned Split-Gate NVM Cell Embedded into 40nm CMOS Logic Process for Automotive Microcontrollers" (PDF). 2016 IEEE 8th International Memory Workshop (IMW). pp. 1–4. doi:10.1109/IMW.2016.7495271. ISBN 978-1-4673-8833-7. S2CID 36398631.
Luo, L. Q.; Teo, Z. Q.; Kong, Y. J.; Deng, F. X.; Liu, J. Q.; Zhang, F.; Cai, X. S.; Tan, K. M.; Lim, K. Y.; Khoo, P.; Jung, S. M.; Siah, S. Y.; Shum, D.; Wang, C. M.; Xing, J. C.; Liu, G. Y.; Diao, Y.; Lin, G. M.; Tee, L.; Lemke, S. M.; Ghazavi, P.; Liu, X.; Do, N.; Pey, K. L.; Shubhakar, K. (May 2016). "Functionality Demonstration of a High-Density 2.5V Self-Aligned Split-Gate NVM Cell Embedded into 40nm CMOS Logic Process for Automotive Microcontrollers" (PDF). 2016 IEEE 8th International Memory Workshop (IMW). pp. 1–4. doi:10.1109/IMW.2016.7495271. ISBN 978-1-4673-8833-7. S2CID 36398631.

sst.com (Global: low place; English: low place)

Broome, Sarah. "Mie Fujitsu and SST Announce Automotive Platform Development on 40nm Technology". www.sst.com. Silicon Storage Technology.

techinsights.com (Global: low place; English: low place)

"NAND Flash Memory Roadmap" (PDF). TechInsights Inc. June 2016. Archived from the original (PDF) on 2018-06-25. Retrieved 2018-03-23.
CHOE, JEONGDONG. "Deep dive into the Intel/Micron 3D 32L FG-NAND". www.techinsights.com.

web.archive.org (Global: 1^st place; English: 1^st place)

"NAND Flash Memory Roadmap" (PDF). TechInsights Inc. June 2016. Archived from the original (PDF) on 2018-06-25. Retrieved 2018-03-23.

worldcat.org (Global: 5^th place; English: 5^th place)

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Chen, P. C. Y. (1977). "Threshold-alterable Si-gate MOS devices". IEEE Transactions on Electron Devices. 24 (5): 584–586. Bibcode:1977ITED...24..584C. doi:10.1109/T-ED.1977.18783. ISSN 0018-9383. S2CID 25586393.
Chen, S. C.; Chang, T. C.; Liu, P. T.; Wu, Y. C.; Lin, P. S.; Tseng, B. H.; Shy, J. H.; Sze, S. M.; Chang, C. Y.; Lien, C. H. (2007). "A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory". IEEE Electron Device Letters. 28 (9): 809–811. Bibcode:2007IEDL...28..809C. doi:10.1109/LED.2007.903885. ISSN 0741-3106. S2CID 40413991.
Lee, M. C.; Wong, H. Y. (2013). "Charge Loss Mechanisms of Nitride-Based Charge Trap Flash Memory Devices". IEEE Transactions on Electron Devices. 60 (10): 3256–3264. Bibcode:2013ITED...60.3256L. doi:10.1109/TED.2013.2279410. ISSN 0018-9383. S2CID 41506023.
Fischer, T.; Nam, B. G.; Chang, L.; Kuroda, T.; Pertijs, M. A. P. (2013). "Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions". IEEE Journal of Solid-State Circuits. 49 (1): 4–8. doi:10.1109/JSSC.2013.2284658. ISSN 0018-9200.
Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L. (31 October 2013). "Solution processed molecular floating gate for flexible flash memories". Scientific Reports. 3 (1). Macmillan Publishers Limited: 3093. Bibcode:2013NatSR...3E3093Z. doi:10.1038/srep03093. ISSN 2045-2322. PMC 3813938. PMID 24172758.

SONOS (English Wikipedia)

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