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harvard.edu
ui.adsabs.harvard.edu
Mahapatra, S.; Vaish, V.; Wasshuber, C.; Banerjee, K.; Ionescu, A.M. (2004). "Analytical Modeling of Single Electron Transistor for Hybrid CMOS-SET Analog IC Design". IEEE Transactions on Electron Devices. 51 (11): 1772–1782. Bibcode:2004ITED...51.1772M. doi:10.1109/TED.2004.837369. ISSN0018-9383. S2CID15373278.
Gubin, S. P.; Gulayev, Yu V.; Khomutov, G. B.; Kislov, V. V.; Kolesov, V. V.; Soldatov, E. S.; Sulaimankulov, K. S.; Trifonov, A. S. (2002). "Molecular clusters as building blocks for nanoelectronics: the first demonstration of a cluster single-electron tunnelling transistor at room temperature". Nanotechnology. 13 (2): 185–194. Bibcode:2002Nanot..13..185G. doi:10.1088/0957-4484/13/2/311..
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Mahapatra, S.; Vaish, V.; Wasshuber, C.; Banerjee, K.; Ionescu, A.M. (2004). "Analytical Modeling of Single Electron Transistor for Hybrid CMOS-SET Analog IC Design". IEEE Transactions on Electron Devices. 51 (11): 1772–1782. Bibcode:2004ITED...51.1772M. doi:10.1109/TED.2004.837369. ISSN0018-9383. S2CID15373278.
Klupfel, F. J.; Burenkov, A.; Lorenz, J. (2016). "Simulation of silicon-dot-based single-electron memory devices". 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). pp. 237–240. doi:10.1109/SISPAD.2016.7605191. ISBN978-1-5090-0818-6. S2CID15721282.
Mahapatra, S.; Vaish, V.; Wasshuber, C.; Banerjee, K.; Ionescu, A.M. (2004). "Analytical Modeling of Single Electron Transistor for Hybrid CMOS-SET Analog IC Design". IEEE Transactions on Electron Devices. 51 (11): 1772–1782. Bibcode:2004ITED...51.1772M. doi:10.1109/TED.2004.837369. ISSN0018-9383. S2CID15373278.