Single instruction, multiple threads (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Single instruction, multiple threads" in English language version.

refsWebsite

Global rank English rank

2nvidia.com

2,503^rd place

1,760^th place

1web.archive.org

1^st place

1dtic.mil

833^rd place

567^th place

1gpgpuarch.org

low place

1fannotes.me

low place

1researchgate.net

120^th place

125^th place

1harvard.edu

18^th place

17^th place

1doi.org

2^nd place

1semanticscholar.org

11^th place

8^th place

1handle.net

102^nd place

76^th place

1khronos.org

9,657^th place

6,690^th place

doi.org (Global: 2^nd place; English: 2^nd place)

Lindholm, Erik; Nickolls, John; Oberman, Stuart; Montrym, John (2008). "NVIDIA Tesla: A Unified Graphics and Computing Architecture". IEEE Micro. 28 (2): 6 (Subscription required.). Bibcode:2008IMicr..28b..39L. doi:10.1109/MM.2008.31. S2CID 2793450.

dtic.mil (Global: 833^rd place; English: 567^th place)

apps.dtic.mil

"An introductory description of the Illiac IV system" (PDF). Archived from the original (PDF) on 2024-04-27.

fannotes.me (Global: low place; English: low place)

"General-Purpose Graphics Processor Architecture - Chapter 3 - The SIMT Core: Instruction and Register Data Flow (Part 1) | FANnotes". www.fannotes.me. Retrieved 2025-07-30.

gpgpuarch.org (Global: low place; English: low place)

"SIMT Model - Open Source General-Purpose Computing Chip Platform - Blue Porcelain(GPGPU)". gpgpuarch.org. Retrieved 2025-07-30.

handle.net (Global: 102^nd place; English: 76^th place)

hdl.handle.net

Rul, Sean; Vandierendonck, Hans; D’Haene, Joris; De Bosschere, Koen (2010). An experimental study on performance portability of OpenCL kernels. Symp. Application Accelerators in High Performance Computing (SAAHPC). hdl:1854/LU-1016024.

harvard.edu (Global: 18^th place; English: 17^th place)

ui.adsabs.harvard.edu

Lindholm, Erik; Nickolls, John; Oberman, Stuart; Montrym, John (2008). "NVIDIA Tesla: A Unified Graphics and Computing Architecture". IEEE Micro. 28 (2): 6 (Subscription required.). Bibcode:2008IMicr..28b..39L. doi:10.1109/MM.2008.31. S2CID 2793450.

khronos.org (Global: 9,657^th place; English: 6,690^th place)

registry.khronos.org

"cl_khr_subgroups(3)". registry.khronos.org.

nvidia.com (Global: 2,503^rd place; English: 1,760^th place)

nvidia.com

"NVIDIA Fermi Compute Architecture Whitepaper" (PDF). www.nvidia.com. NVIDIA Corporation. 2009. Retrieved 2014-07-17.

developer.nvidia.com

"Faster Parallel Reductions on Kepler". NVIDIA Technical Blog. February 14, 2014.

researchgate.net (Global: 120^th place; English: 125^th place)

"The Illiac IV system".

semanticscholar.org (Global: 11^th place; English: 8^th place)

api.semanticscholar.org

Lindholm, Erik; Nickolls, John; Oberman, Stuart; Montrym, John (2008). "NVIDIA Tesla: A Unified Graphics and Computing Architecture". IEEE Micro. 28 (2): 6 (Subscription required.). Bibcode:2008IMicr..28b..39L. doi:10.1109/MM.2008.31. S2CID 2793450.

web.archive.org (Global: 1^st place; English: 1^st place)

"An introductory description of the Illiac IV system" (PDF). Archived from the original (PDF) on 2024-04-27.

Single instruction, multiple threads (English Wikipedia)

doi.org (Global: 2nd place; English: 2nd place)

dtic.mil (Global: 833rd place; English: 567th place)