Through-silicon via (English Wikipedia)

Analysis of information sources in references of the Wikipedia article "Through-silicon via" in English language version.

refsWebsite

Global rank English rank

7doi.org

2^nd place

5semanticscholar.org

11^th place

8^th place

3books.google.com

3^rd place

23dincites.com

low place

2patents.google.com

1,182^nd place

725^th place

2web.archive.org

1^st place

1semiconductors.org

low place

1jedec.org

low place

7,755^th place

1sematech.org

low place

1arxiv.org

69^th place

59^th place

1harvard.edu

18^th place

17^th place

1skhynix.com

low place

3dincites.com

Von Trapp, Francoise (15 September 2014). "The Future of Image Sensors is Chip Stacking". 3D InCites.
Von Trapp, Francoise (24 April 2010). "Who Invented the TSV and When?". 3D InCites.

arxiv.org

Macchiolo, A.; Andricek, L.; Moser, H. G.; Nisius, R.; Richter, R. H.; Weigell, P. (1 January 2012). "SLID-ICV Vertical Integration Technology for the ATLAS Pixel Upgrades". Physics Procedia. 37: 1009–1015. arXiv:1202.6497. Bibcode:2012PhPro..37.1009M. doi:10.1016/j.phpro.2012.02.444. S2CID 91179768.

books.google.com

Pavlidis, Vasilis F.; Savidis, Ioannis; Friedman, Eby G. (2017). Three-Dimensional Integrated Circuit Design. Newnes. p. 68. ISBN 978-0-12-410484-6.
Takahashi, Kenji; Tanida, Kazumasa (2011). "Vertical Interconnection by ASET". Handbook of 3D Integration. Vol. 1: Technology and Applications of 3D Integrated Circuits. John Wiley & Sons. p. 339. ISBN 978-3-527-62306-8.
Kada, Morihiro (2015). "Research and Development History of Three-Dimensional Integration Technology". Three-Dimensional Integration of Semiconductors: Processing, Materials, and Applications. Springer. pp. 15–8. ISBN 978-3-319-18675-7.

doi.org

Knechtel, Johann; Sinanoglu, Ozgur; Elfadel, Ibrahim (Abe) M.; Lienig, Jens; Sze, Cliff C. N. (2017). "Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration". IPSJ Transactions on System LSI Design Methodology. 10: 45–62. doi:10.2197/ipsjtsldm.10.45.
Beyne, Eric (2016). "The 3-D Interconnect Technology Landscape". IEEE Design & Test. 33 (3): 8–20. doi:10.1109/mdat.2016.2544837. S2CID 29564868.
Lim, Sung Kyu (2013). Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. doi:10.1007/978-1-4419-9542-1. ISBN 978-1-4419-9541-4.
Kada, Morihiro (2015). "Research and Development History of Three-Dimensional Integration Technology". Three-Dimensional Integration of Semiconductors. pp. 1–23. doi:10.1007/978-3-319-18675-7_1. ISBN 978-3-319-18674-0.
Ramm, P.; Bollmann, D.; Braun, R.; Buchner, R.; Cao-Minh, U.; et al. (November 1997). "Three dimensional metallization for vertically integrated circuits". Microelectronic Engineering. 37–38: 39–47. doi:10.1016/S0167-9317(97)00092-0. S2CID 22232571.
Macchiolo, A.; Andricek, L.; Moser, H. G.; Nisius, R.; Richter, R. H.; Weigell, P. (1 January 2012). "SLID-ICV Vertical Integration Technology for the ATLAS Pixel Upgrades". Physics Procedia. 37: 1009–1015. arXiv:1202.6497. Bibcode:2012PhPro..37.1009M. doi:10.1016/j.phpro.2012.02.444. S2CID 91179768.
Savastionk, S.; Siniaguine, O.; Korczynski, E. (2000). "Thru-silicon vias for 3D WLP". Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.00TH8507). pp. 206–207. doi:10.1109/ISAPM.2000.869271. ISBN 0-930815-59-9. S2CID 110397071.

harvard.edu

ui.adsabs.harvard.edu

Macchiolo, A.; Andricek, L.; Moser, H. G.; Nisius, R.; Richter, R. H.; Weigell, P. (1 January 2012). "SLID-ICV Vertical Integration Technology for the ATLAS Pixel Upgrades". Physics Procedia. 37: 1009–1015. arXiv:1202.6497. Bibcode:2012PhPro..37.1009M. doi:10.1016/j.phpro.2012.02.444. S2CID 91179768.

jedec.org

"JEDEC Publishes Breakthrough Standard for Wide I/O Mobile DRAM". JEDEC (Press release). Arlington, VA. 5 January 2012. Retrieved 1 December 2014.

patents.google.com

semanticscholar.org

api.semanticscholar.org

Beyne, Eric (2016). "The 3-D Interconnect Technology Landscape". IEEE Design & Test. 33 (3): 8–20. doi:10.1109/mdat.2016.2544837. S2CID 29564868.
Tanaka, Tetsu; Lee, Kang Wook; Fukushima, Takafumi; Koyanagi, Mitsumasa (2011). 3D Integration Technology and Heterogeneous Integration (Report). S2CID 62780117.
Ramm, P.; Bollmann, D.; Braun, R.; Buchner, R.; Cao-Minh, U.; et al. (November 1997). "Three dimensional metallization for vertically integrated circuits". Microelectronic Engineering. 37–38: 39–47. doi:10.1016/S0167-9317(97)00092-0. S2CID 22232571.
Macchiolo, A.; Andricek, L.; Moser, H. G.; Nisius, R.; Richter, R. H.; Weigell, P. (1 January 2012). "SLID-ICV Vertical Integration Technology for the ATLAS Pixel Upgrades". Physics Procedia. 37: 1009–1015. arXiv:1202.6497. Bibcode:2012PhPro..37.1009M. doi:10.1016/j.phpro.2012.02.444. S2CID 91179768.
Savastionk, S.; Siniaguine, O.; Korczynski, E. (2000). "Thru-silicon vias for 3D WLP". Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.00TH8507). pp. 206–207. doi:10.1109/ISAPM.2000.869271. ISBN 0-930815-59-9. S2CID 110397071.

sematech.org

Fukushima, T.; Tanaka, T.; Koyanagi, Mitsumasa (2007). "Thermal Issues of 3D ICs" (PDF). SEMATECH. Tohoku University. Archived from the original (PDF) on 16 May 2017. Retrieved 16 May 2017.

semiconductors.org

2009 International Technology Roadmap for Semiconductors (ITRS). 5 September 2009. pp. 4–5.

skhynix.com

"History: 2010s". SK Hynix. Archived from the original on 17 May 2021. Retrieved 19 July 2019.

web.archive.org

Fukushima, T.; Tanaka, T.; Koyanagi, Mitsumasa (2007). "Thermal Issues of 3D ICs" (PDF). SEMATECH. Tohoku University. Archived from the original (PDF) on 16 May 2017. Retrieved 16 May 2017.
"History: 2010s". SK Hynix. Archived from the original on 17 May 2021. Retrieved 19 July 2019.