Transactional Synchronization Extensions (English Wikipedia)

Johan De Gelas (2012-09-20). "Making Sense of the Intel Haswell Transactional Synchronization eXtensions". AnandTech. Archived from the original on September 22, 2012. Retrieved 2013-10-20.
De Gelas, Johan (September 20, 2012). "Making Sense of the Intel Haswell Transactional Synchronization eXtensions". AnandTech. Archived from the original on December 23, 2013. Retrieved 23 December 2013. The whole "CPU does the fine grained locks" is based upon tagging the L1 (64 B) cachelines and there are 512 of them to be specific (64 x 512 = 32 KB). There is only one "lock tag" per cacheline.
Ian Cutress (2014-08-12). "Intel Disables TSX Instructions: Erratum Found in Haswell, Haswell-E/EP, Broadwell-Y". AnandTech. Archived from the original on August 14, 2014. Retrieved 2014-08-30.

archive.today (Global: 14^th place; English: 14^th place)

De Gelas, Johan (September 20, 2012). "Making Sense of the Intel Haswell Transactional Synchronization eXtensions". AnandTech. Archived from the original on December 23, 2013. Retrieved 23 December 2013. The whole "CPU does the fine grained locks" is based upon tagging the L1 (64 B) cachelines and there are 512 of them to be specific (64 x 512 = 32 KB). There is only one "lock tag" per cacheline.

arstechnica.com (Global: 388^th place; English: 265^th place)

"Transactional memory going mainstream with Intel Haswell". Ars Technica. 2012-02-08. Retrieved 2012-02-09.

blackhat.com (Global: low place; English: low place)

"Breaking Kernel Address Space Layout Randomization with Intel TSX" (PDF). 2016.

hipeac.net (Global: low place; English: low place)

"HiPEAC info" (PDF). p. 12. Archived from the original (PDF) on 2017-03-05.

intel-research.net (Global: low place; English: low place)

pcl.intel-research.net

Richard M. Yoo; Christopher J. Hughes; Konrad Lai; Ravi Rajwar (November 2013). "Performance Evaluation of Intel Transactional Synchronization Extensions for High-Performance Computing" (PDF). intel-research.net. Archived from the original (PDF) on 2016-10-24. Retrieved 2013-11-14.

intel.com (Global: 1,118^th place; English: 825^th place)

intel.com

"Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium Processor Family, and Desktop Intel Celeron Processor Family: Specification Update (Revision 014)" (PDF). Intel. June 2014. p. 46. Retrieved 2014-08-13. Under a complex set of internal timing conditions and system events, software using the Intel TSX/TSX-NI (Transactional Synchronization Extensions) instructions may observe unpredictable system behavior.
"Compare Products". Intel. Retrieved 2025-03-10.
"Intel 64 and IA-32 Architectures Software Developer's Manual Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B, and 3C" (PDF). Intel. September 2013. p. 342. Retrieved 2013-11-19.
"Intel 64 and IA-32 Architectures Optimization Reference Manual" (PDF). Intel. September 2013. p. 446. Retrieved 2013-11-19.
"Intel Core M Processor Family. Specification Update. December 2014. Revision 003. 330836-003" (PDF). Intel. December 2014. p. 10. Retrieved 2014-12-28. BDM53 ¹ E-0: X, F-0:, Status: Fixed ERRATA: Intel TSX Instructions Not Available. 1. Applies to Intel Core M-5Y70 processor. Intel TSX is supported on Intel Core M-5Y70 processor with Intel vPro Technology. Intel TSX is not supported on other processor SKUs.
"Performance Monitoring Impact of Intel® Transactional Synchronization Extension Memory Ordering Issue White Paper, June 2021, Revision 1.4" (PDF). Intel. 2021-06-12. p. 5. The October 2018 microcode update also disabled the HLE instruction prefix of Intel TSX and force all RTM transactions to abort when operating in Intel SGX mode or System Management Mode (SMM).
"Intel® Transactional Synchronization Extensions (Intel® TSX) Memory and Performance Monitoring Update for Intel® Processors". Intel. 2021-06-12.

software.intel.com

Tomas Karnagel; Roman Dementiev; Ravi Rajwar; Konrad Lai; Thomas Legler; Benjamin Schlegel; Wolfgang Lehner (February 2014). "Improving In-Memory Database Index Performance with Intel Transactional Synchronization Extensions" (PDF). software.intel.com. Retrieved 2014-03-03.
"Transactional Synchronization in Haswell". Software.intel.com. Archived from the original on 2020-02-23. Retrieved 2012-02-07.
Wooyoung Kim (2013-07-25). "Fun with Intel Transactional Synchronization Extensions". Intel. Retrieved 2013-11-12.
"Hardware Lock Elision Overview". intel.com. Archived from the original on 2013-10-29. Retrieved 2013-10-27.
"Intel TSX implementation properties". Intel. 2013. Retrieved 2013-11-14. The processor tracks both the read-set addresses and the write-set addresses in the first level data cache (L1 cache) of the processor.
"Intel® Architecture Instruction Set Extensions Programming Reference" (PDF). Intel. 2020. Retrieved 2020-10-21.

ark.intel.com

"Intel Comparison Table of Haswell Pentium, i3, i5, and i7 models". intel.com. Retrieved 2014-02-11.
"Intel® Core™ i9-10900K Processor specifications". Intel. 2020. Retrieved 2020-10-10.
"Intel® Core™ i9-10980HK Processor specifications". Intel. 2020. Retrieved 2020-10-10.
"Intel® Core™ i7-10810U Processor specifications". Intel. 2020. Retrieved 2020-10-10.
"Intel® Xeon® W-1290P Processor specifications". Intel. 2020. Retrieved 2020-10-10.
"Intel® Core™ i7-1068NG7 Processor specifications". Intel. 2020. Retrieved 2020-10-10.

mit.edu (Global: 415^th place; English: 327^th place)

people.csail.mit.edu

Sebastien Dabdoub; Stephen Tu. "Supporting Intel Transactional Synchronization Extensions in QEMU" (PDF). mit.edu. Retrieved 2013-11-12.

realworldtech.com (Global: low place; English: low place)

David Kanter (2012-08-21). "Analysis of Haswell's Transactional Memory". Real World Technologies. Retrieved 2013-11-19.
David Kanter (2012-08-21). "Haswell Transactional Memory Alternatives". Real World Technologies. Retrieved 2013-11-14.

sisoftware.co.uk (Global: low place; English: low place)

"Benchmarks: Haswell's TSX and Memory Transaction Throughput (HLE and RTM)". sisoftware.co.uk. Retrieved 2013-11-14.

supercomputing.org (Global: low place; English: low place)

sc13.supercomputing.org

"Performance Evaluation of Intel Transactional Synchronization Extensions for High Performance Computing". supercomputing.org. November 2013. Archived from the original on 2013-10-29. Retrieved 2013-11-14.

techreport.com (Global: low place; English: 6,965^th place)

Scott Wasson (2014-08-12). "Errata prompts Intel to disable TSX in Haswell, early Broadwell CPUs". techreport.com. Retrieved 2014-08-12.

theregister.com (Global: 3,700^th place; English: 2,360^th place)

Gareth Halfacree (2021-06-29). "Intel sticks another nail in the coffin of TSX with feature-disabling microcode update". The Register. Retrieved 2012-10-17.

tomshardware.com (Global: 2,976^th place; English: 1,939^th place)

"The Core i7-4770K Review". Tom's Hardware. 2013-06-01. Retrieved 2012-06-03.

web.archive.org (Global: 1^st place; English: 1^st place)

Richard M. Yoo; Christopher J. Hughes; Konrad Lai; Ravi Rajwar (November 2013). "Performance Evaluation of Intel Transactional Synchronization Extensions for High-Performance Computing" (PDF). intel-research.net. Archived from the original (PDF) on 2016-10-24. Retrieved 2013-11-14.
"Performance Evaluation of Intel Transactional Synchronization Extensions for High Performance Computing". supercomputing.org. November 2013. Archived from the original on 2013-10-29. Retrieved 2013-11-14.
"Transactional Synchronization in Haswell". Software.intel.com. Archived from the original on 2020-02-23. Retrieved 2012-02-07.
Johan De Gelas (2012-09-20). "Making Sense of the Intel Haswell Transactional Synchronization eXtensions". AnandTech. Archived from the original on September 22, 2012. Retrieved 2013-10-20.
"Hardware Lock Elision Overview". intel.com. Archived from the original on 2013-10-29. Retrieved 2013-10-27.
Ian Cutress (2014-08-12). "Intel Disables TSX Instructions: Erratum Found in Haswell, Haswell-E/EP, Broadwell-Y". AnandTech. Archived from the original on August 14, 2014. Retrieved 2014-08-30.
"HiPEAC info" (PDF). p. 12. Archived from the original (PDF) on 2017-03-05.

Transactional Synchronization Extensions (English Wikipedia)

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