Analysis of information sources in references of the Wikipedia article "X86 instruction listings" in English language version.
UD1 instruction on page 356. Archived on 29 Dec 2024.CMPXCHG with 0F A6/A7 encodings.CMPXCHG with 0F B0/B1 encodings.0F 0B and 0F B9.OIO ("Official invalid opcode") for the 0F FF opcode.0F FF opcode without assigning it a mnemonic.FXTRACT special-cases and section 4.4.9 on page 87 for information about the FPTAN (and by extension FSIN/FCOS/FSINCOS) argument reduction inaccuracy.internal (zero-)extending the value of a smaller (16-bit) register … applying the bswap to a 32-bit value "00 00 AH AL", … truncated to lower 16-bits, which are "00 00". … Bochs … bswap reg16 acts just like the bswap reg32 … QEMU … ignores the 66h prefix
MONITOR/MWAIT mnemonics. Archived on 6 Nov 2022.CR0, it is specifically necessary to do a far JMP (opcode EA) in order to restore proper real-mode access-rights for the CS segment, and that other far control transfers (e.g. RETF, IRET) will not do this. Archived on 4 Nov 2024.SALC on page 83, INT1 on page 86 and FFREEP on page 114. Archived from the original on 22 Dec 1996.MFENCE;LFENCE sequence to enforce ordering between a memory store and a later x2apic MSR write. Archived on 4 Jul 2024HWNT/HST mnemonics for the branch hint prefixes. Archived from the original on 5 Feb 2005.CPUID instruction)RDTSC instruction on p.1739 describes the instruction sequences required to order the RDTSC instruction with respect to earlier and later instructions.UD0 and page 415 and 419 for UD1.UD1 (with ModR/M byte) and UD0 (without ModR/M byte) on page 4-687.UD0 (with ModR/M byte) on page 4-683.FSIN, FCOS, FSINCOS and FPTAN in volume 1, section 8.3.8NOP instruction description.)UD0 and UD1.The instruction brings down the upper word of the doubleword register without affecting its upper 16 bits.
Using the REP or REPNE prefix with a MUL or IMUL instruction negates the product. Using the REP or REPNE prefix with an IDIV instruction negates the quotient.
MONITOR and MWAIT with explicit operands. Archived on 9 May 2005.UD2A and UD2B instruction mnemomics to GNU Binutils. Archived on 25 Jul 2023.UD1/UD2B and added UD0. Archived on 25 Jul 2023.CR0, it is specifically necessary to do a far JMP (opcode EA) in order to restore proper real-mode access-rights for the CS segment, and that other far control transfers (e.g. RETF, IRET) will not do this. Archived on 4 Nov 2024.SALC on page 83, INT1 on page 86 and FFREEP on page 114. Archived from the original on 22 Dec 1996.The instruction brings down the upper word of the doubleword register without affecting its upper 16 bits.
UD2A and UD2B instruction mnemomics to GNU Binutils. Archived on 25 Jul 2023.UD1/UD2B and added UD0. Archived on 25 Jul 2023.UD1 instruction on page 356. Archived on 29 Dec 2024.MFENCE;LFENCE sequence to enforce ordering between a memory store and a later x2apic MSR write. Archived on 4 Jul 2024MONITOR and MWAIT with explicit operands. Archived on 9 May 2005.MONITOR/MWAIT mnemonics. Archived on 6 Nov 2022.HWNT/HST mnemonics for the branch hint prefixes. Archived from the original on 5 Feb 2005.Using the REP or REPNE prefix with a MUL or IMUL instruction negates the product. Using the REP or REPNE prefix with an IDIV instruction negates the quotient.
0F 0A for SCC's message invalidation instruction.