«H87I-PLUS». Asus. «Esta placa base permite conectar hasta tres monitores independientes en las salidas vídeo DisplayPort, Mini DisplayPort, HDMI, DVI y VGA. Podrás configurarlos en los modos espejo y collage.»
David Galus. «Migration to New Display Technologies on Intel Embedded Platforms»(en inglés). «The Intel® 7 Series Chipset based platform allows for the support of up to three concurrent displays with independent or replicated content. However, this comes with the requirement that either one of the displays is eDP running off the CPU or two DP interfaces are being used off the PCH. When configuring the 2 DP interfaces from the PCH, one may be an eDP if using Port D. This limitation exists because the 7 Series Intel PCH contains only two display PLLs (the CPU has one display PLL also) which will control the clocking for the respective displays. All display types other than DP have an external variable clock frequency associated with the display resolution that is being used. The DP interface has an embedded clocking scheme that is semi- variable, either at 162 or 270 MHz depending on the bandwidth required. Therefore, Intel only allows sharing of a display PLL with DP related interfaces.»|autor= y |apellido= redundantes (ayuda)
«Migration to New Display Technologies on Intel Embedded Platforms»(en inglés). Intel. February 2013. «The Intel® 7 Series Chipset based platform allows for the support of up to three concurrent displays with independent or replicated content. However, this comes with the requirement that either one of the displays is eDP running off the CPU or two DP interfaces are being used off the PCH. When configuring the 2 DP interfaces from the PCH, one may be an eDP if using Port D. This limitation exists because the 7 Series Intel PCH contains only two display PLLs (the CPU has one display PLL also) which will control the clocking for the respective displays. All display types other than DP have an external variable clock frequency associated with the display resolution that is being used. The DP interface has an embedded clocking scheme that is semi- variable, either at 162 or 270 MHz depending on the bandwidth required. Therefore, Intel only allows sharing of a display PLL with DP related interfaces.»
Michael Larabel (6 de octubre de 2011). «Details On Intel Ivy Bridge Triple Monitor Support»(en inglés). «A limitation of this triple monitor support for Ivy Bridge is that two of the pipes need to share a PLL. Ivy Bridge has three planes, three pipes, three transcoders, and three FDI (Flexible Display Interface) interfaces for this triple monitor support, but there's only two pipe PLLs. This means that two of the three outputs need to have the same connection type and same timings. However, most people in a triple monitor environment will have at least two — if not all three — of the monitors be identical and configured the same, so this shouldn't be a terribly huge issue.»
