Dissipation de puissance du processeur (French Wikipedia)

Analysis of information sources in references of the Wikipedia article "Dissipation de puissance du processeur" in French language version.

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3doi.org

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2semanticscholar.org

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325^th place

1microsoft.com

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1academia.edu

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1anandtech.com

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1intel.com

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1books.google.com

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1scarpaz.com

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1psu.edu

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1northwestern.edu

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1gotw.ca

low place

academia.edu

(en) Sparsh Mittal et Jeffrey S. Vetter, « A Survey of Methods for Analyzing and Improving GPU Energy Efficiency », ACM Computing Surveys, vol. 47, n^o 2,‎ 2014 (DOI 10.1145/2636342, lire en ligne)

anandtech.com

(en) Ian Cutress, « Undervolting and Overclocking on Ivy Bridge », sur anandtech.com, 23 avril 2012

books.google.com

(en) "Low Power Design Methodologies", Jan M. Rabaey; Massoud Pedram, 2012 (résumé)

doi.org

dx.doi.org

(en) Sparsh Mittal et Jeffrey S. Vetter, « A Survey of Methods for Analyzing and Improving GPU Energy Efficiency », ACM Computing Surveys, vol. 47, n^o 2,‎ 2014 (DOI 10.1145/2636342, lire en ligne)
(en) K. Basu, A. Choudhary, J. Pisharath et M. Kandemir « Power protocol: Reducing power dissipation on off-chip data buses » (2002) (DOI 10.1109/MICRO.2002.1176262, S2CID 18811466, CiteSeer^x 10.1.1.115.9946, lire en ligne)
—35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings.
(en) K. Moiseev, A. Kolodny and S. Wimer, « Timing-aware power-optimal ordering of signals », ACM Transactions on Design Automation of Electronic Systems, vol. 13, n^o 4,‎ septembre 2008, p. 1–17 (DOI 10.1145/1391962.1391973, S2CID 18895687)

gotw.ca

(en) Herb Sutter, « The Free Lunch Is Over: A Fundamental Turn Toward Concurrency in Software », Dr. Dobb's Journal, vol. 30, n^o 3,‎ 2005 (lire en ligne)

intel.com

download.intel.com

(en) « Enhanced Intel SpeedStep Technology for the Intel Pentium M Processor (White Paper) », Intel Corporation, mars 2004 (consulté le 21 décembre 2013)

microsoft.com

(en) Yifan Zhang, Yunxin Liu, Li Zhuang, Xuanzhe Liu, Feng Zhao et Qun Li, Accurate CPU Power Modeling for Multicore Smartphones, Microsoft Research (lire en ligne)

northwestern.edu

cucis.eecs.northwestern.edu

(en) K. Basu, A. Choudhary, J. Pisharath et M. Kandemir « Power protocol: Reducing power dissipation on off-chip data buses » (2002) (DOI 10.1109/MICRO.2002.1176262, S2CID 18811466, CiteSeer^x 10.1.1.115.9946, lire en ligne)
—35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings.

psu.edu

citeseerx.ist.psu.edu

(en) K. Basu, A. Choudhary, J. Pisharath et M. Kandemir « Power protocol: Reducing power dissipation on off-chip data buses » (2002) (DOI 10.1109/MICRO.2002.1176262, S2CID 18811466, CiteSeer^x 10.1.1.115.9946, lire en ligne)
—35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings.

scarpaz.com

(en) Ching-Long Su, Chi-Ying Tsui et Alvin M. Despain, Low Power Architecture Design and Compilation Techniques for High-Performance Processors, Advanced Computer Architecture Laboratory, 1994 (lire en ligne)

semanticscholar.org

api.semanticscholar.org

(en) K. Basu, A. Choudhary, J. Pisharath et M. Kandemir « Power protocol: Reducing power dissipation on off-chip data buses » (2002) (DOI 10.1109/MICRO.2002.1176262, S2CID 18811466, CiteSeer^x 10.1.1.115.9946, lire en ligne)
—35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings.
(en) K. Moiseev, A. Kolodny and S. Wimer, « Timing-aware power-optimal ordering of signals », ACM Transactions on Design Automation of Electronic Systems, vol. 13, n^o 4,‎ septembre 2008, p. 1–17 (DOI 10.1145/1391962.1391973, S2CID 18895687)