Proses 5 nm (Indonesian Wikipedia)

Analysis of information sources in references of the Wikipedia article "Proses 5 nm" in Indonesian language version.

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  • Doris, Bruce B.; Dokumaci, Omer H.; Ieong, Meikei K.; Mocuta, Anda; Zhang, Ying; Kanarsky, Thomas S.; Roy, R. A. (December 2002). Extreme scaling with ultra-thin Si channel MOSFETs. Digest. International Electron Devices Meeting. hlm. 267–270. doi:10.1109/IEDM.2002.1175829. ISBN 0-7803-7462-2. 
  • Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). Sub-10-nm planar-bulk-CMOS devices using lateral junction control. IEEE International Electron Devices Meeting 2003. hlm. 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446. ISBN 0-7803-7872-5. 
  • J.C. Liu; et al. A Reliability Enhanced 5nm CMOS Technology Featuring 5th Generation FinFET with Fully-Developed EUV and High Mobility Channel for Mobile SoC and High Performance Computing Application. 2020 IEEE International Electron Devices Meeting (IEDM). doi:10.1109/IEDM13553.2020.9372009. 

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  • "Quantum Effects At 7/5nm And Beyond". Semiconductor Engineering (dalam bahasa Inggris). Diarsipkan dari versi asli tanggal 15 July 2018. Diakses tanggal 2018-07-15. 
  • Mark LaPedus (2016-01-20). "5nm Fab Challenges". Diarsipkan dari versi asli tanggal 27 January 2016. Diakses tanggal 22 January 2016. Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS). 

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