Memoria cache (Italian Wikipedia)

Analysis of information sources in references of the Wikipedia article "Memoria cache" in Italian language version.

refsWebsite

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16web.archive.org

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9google.com

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6freepatentsonline.com

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6google.it

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2amd.com

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2wustl.edu

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2sourceforge.net

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2uva.es

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1britannica.com

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1merriam-webster.com

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1uah.edu

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1anandtech.com

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1freebsd.org

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1inria.fr

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1researchgate.net

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1umich.edu

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1ctho.org

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1pccomponents.com

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1intel.ie

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1aminer.org

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1freescale.com

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1vt.edu

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1realworldtech.com

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1llnl.gov

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1dba-oracle.com

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1auckland.ac.nz

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1wisc.edu

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1ibm.com

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1umd.edu

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amd.com

developer.amd.com

Architecture Programmer’s Manual "3.9.4 Cache Operation" - http://developer.amd.com/wordpress/media/2012/10/24593_APM_v21.pdf Archiviato il 3 marzo 2016 in Internet Archive.
AMD64 Technology - AMD64 Architecture Programmer's Manual Volume 2: System Programming - http://developer.amd.com/wordpress/media/2012/10/24593_APM_v21.pdf Archiviato il 3 marzo 2016 in Internet Archive.

aminer.org

pdf.aminer.org

Sweazey, P., and Smith, A. J. A class of compatible cache consistency protocols and their support by the IEEE Futurebus. In Proceedings of the 13th International Symposium on Computer Architecture. IEEE. New York, 1986, pp. 414-423.) - http://pdf.aminer.org/000/419/524/a_class_of_compatible_cache_consistency_protocols_and_their_support.pdf

anandtech.com

Intel Iris Pro 5200 Graphics Review: Core i7-4950HQ Tested - https://www.anandtech.com/show/6993/intel-iris-pro-5200-graphics-review-core-i74950hq-tested/3

auckland.ac.nz

cs.auckland.ac.nz

A new Solution to Coherence Problems in Multicaches Systems - Censier and Feaultrier - http://www.cs.auckland.ac.nz/courses/compsci703s1c/resources/Censier.pdf

britannica.com

https://www.britannica.com/technology/cache-memory

ctho.org

Archibald, J. and Baer, J. 1986 - Cache coherence protocols: evaluation using a multiprocessor simulation model. ACM Trans. Comput. Syst. 4, 4 (Sep. 1986), 273-298) - http://ctho.org/toread/forclass/18-742/3/p273-archibald.pdf

dba-oracle.com

NUMA Architecture - http://www.dba-oracle.com/real_application_clusters_rac_grid/numa.html Archiviato il 9 ottobre 2016 in Internet Archive.

freebsd.org

people.freebsd.org

Comparing Cache Architectures and Coherency Protocols on x86-64 Multicore SMP Systems - https://people.freebsd.org/~lstewart/articles/cache-performance-x86-2009.pdf

freepatentsonline.com

FPO IP Research & Communities
FPO IP Research & Communities
FPO IP Research & Communities
Multi-processor system with shared memory - http://www.freepatentsonline.com/5701413.html
Bull HN F. Zulian - A. Zulian patent - Computer system with a bus having a segmented structure - http://www.freepatentsonline.com/6314484.html
(EN) Data-processing system with CC-NUMA (cache-coherent, non-uniform memory access) architecture and remote cache incorporated in local memory, su freepatentsonline.com.

freescale.com

MPC750UM/D 12/2001 Rev. 1 MPC750 RISC Microprocessor Family User's Manual - http://www.freescale.com/files/32bit/doc/ref_manual/MPC750UM.pdf Archiviato il 24 settembre 2015 in Internet Archive.

gatech.edu

cc.gatech.edu

"POWER4 System Microarchitecture", http://www.cc.gatech.edu/~bader/COURSES/UNM/ece637-Fall2003/papers/TDF02.pdf Archiviato il 7 novembre 2013 in Internet Archive.

google.com

Ravi Kumar Arimilli, John Steven Dodson e John Michael Kaiser, Cache-coherency protocol with recently read state for data and instructions, US5996049 A, 30 novembre 1999. URL consultato il 28 febbraio 2017.
Herbert H. J. Hum e James R. Goodman, Forward state for use in cache coherency in a multiprocessor system, US6922756 B2, 26 luglio 2005. URL consultato il 28 febbraio 2017.
Cache Ccoherency Protocol Including an HR State - IBM patent - https://www.google.com/patents/US6275908
Ravi Kumar Arimilli, John Steven Dodson e Jerry Don Lewis, Cache coherency protocol with tagged state for modified values, US6334172 B1, 25 dicembre 2001. URL consultato il 28 febbraio 2017.
Ravi Kumar Arimilli, John Steven Dodson e Jerry Don Lewis, Cache coherency protocol including an HR state, US6275908 B1, Aug 14, 2001. URL consultato il 28 febbraio 2017.
Cache-coherency protocol with recently read state for data and instructions - IBM patent - https://www.google.com/patents/US5996049
Cache Coherency Protocol with Tagged State for Modified Values - IBM patent - https://www.google.com/patents/US6334172
Cache memory and related consistency protocol, Inventor Ferruccio Zulian, Bull HN ISI - https://www.google.com/patents/EP0396940B1?cl=en
Cache memory having pseudo virtual addressing - Honeywell Bull Italia - https://www.google.com/patents/US5165028

google.com.tr

High-speed memory and memory management system - Sun Microsystems, su google.com.tr.

google.it

books.google.it

Handy, Jim. "Cache Memory Book", Academic Press, Inc., 1998, p. 130, p. 208 - http://books.google.it/books?hl=it&id=-7oOlb-lCpMC&q=208
Pentium Pro and Pentium II System Architecture pg. 160 - Di T. Shanley - http://books.google.it/books?id=MLJClvCYh34C&pg=PA160&lpg=PA160&dq=Pentium+protocol+cache&source=bl&ots=gaOu-EvaTy&sig=QQEM1krp-H_0KUhi5Ti2bmxU2kU&hl=it&sa=X&ei=Zt6KT7icG8TE4gShzaDwCQ&ved=0CDcQ6AEwAg#v=onepage&q=Pentium%20protocol%20cache&f=false
Advanced Computer Architecture, 2E pg. 301 - Di Hwang - http://books.google.it/books?id=m4VFXr6qjroC&pg=PA301&lpg=PR10&focus=viewport&dq=Multiprocessors+and+Multicomputers+7.2+Cache+Coherence+and+Synchronization&hl=it

scholar.google.it

google.it

Method for transferring data in a multiprocessor computer system with crossbar interconnecting unit - https://www.google.it/patents/EP0923032A1?cl=en

ibm.com

www-03.ibm.com

Of NUMA on POWER7 in IBM - https://www-03.ibm.com/systems/resources/pwrsysperf_P7NUMA.pdf

inria.fr

pages.saclay.inria.fr

Data Caches for Superscalar Processors - http://pages.saclay.inria.fr/olivier.temam/files/eval/JNT97.pdf

intel.ie

An Introduction to the Intel® QuickPath Interconnect - http://www.intel.ie/content/dam/doc/white-paper/quick-path-interconnect-introduction-paper.pdf

llnl.gov

computing.llnl.gov

IBM POWER Systems Overview - https://computing.llnl.gov/tutorials/ibm_sp/ Archiviato il 27 maggio 2010 in Internet Archive.

merriam-webster.com

https://www.merriam-webster.com/dictionary/cache

pccomponents.com

MPC7400 RISC Microprocessor User's Manual - http://pccomponents.com/datasheets/MOT-MPC7400.PDF

realworldtech.com

David Kanter, The Common System Interface: Intel’s Future Interconnect, in Real World Tech, 28 agosto 2007, p. 5. URL consultato il 12 agosto 2012.

researchgate.net

Comparing Multiported Cache Schemes - https://www.researchgate.net/publication/221134115_Comparing_Multiported_Cache_Schemes/file/32bfe50fb1759c4f80.pdf

sourceforge.net

lse.sourceforge.net

SourceForge - http://lse.sourceforge.net/numa/faq/system_descriptions.html
SourceForge - http://lse.sourceforge.net/numa/faq/

tomshardware.com

(EN) Athlon II Or Phenom II: Does Your CPU Need L3 Cache?, in Tom's Hardware, 6 ottobre 2009. URL consultato il 28 febbraio 2017.

uah.edu

ece.uah.edu

Performance Evaluation of Cache Replacement Policies for the SPEC CPU2000 Benchmark Suite (PDF), su ece.uah.edu.

umd.edu

ece.umd.edu

Virtual-Address Caches (PDF), su ece.umd.edu.

umich.edu

web.eecs.umich.edu

On High-Bandwidth Data Cache Design for Multi-Issue Processors - https://web.eecs.umich.edu/~taustin/papers/MICRO30-bwcache.pdf

uva.es

dte.eis.uva.es

Directory-based CacheCoherence – Parallel Computer Architecture par. 1.3.2 pg. 48 – http://www.dte.eis.uva.es/Docencia/ETSII/SMP/archivos/archibak/culler.pdf Archiviato il 18 maggio 2015 in Internet Archive.
Directory-based CacheCoherence - Parallel Computer Architecture ch. 8 pg. 513 - http://www.dte.eis.uva.es/Docencia/ETSII/SMP/archivos/archibak/culler.pdf Archiviato il 18 maggio 2015 in Internet Archive.

vt.edu

courses.cs.vt.edu

Using cache memory to reduce processor-memory traffic". Proceedings of the 10th annual international symposium on Computer architecture - ISCA '83. International Symposium on Computer Architecture: Stockholm, Sweden, June 13–17, 1983.pp. 127-128 - http://courses.cs.vt.edu/cs5204/fall11-kafura/Papers/TransactionalMemory/Goodman-SnoopyProtocol.pdf

web.archive.org

The POWER4 Processor Introduction and Tuning Guide par. 2.4 - Copia archiviata (PDF), su web.eecs.utk.edu. URL consultato il 26 settembre 2014 (archiviato dall'url originale il 6 dicembre 2014).
Architecture Programmer’s Manual "3.9.4 Cache Operation" - http://developer.amd.com/wordpress/media/2012/10/24593_APM_v21.pdf Archiviato il 3 marzo 2016 in Internet Archive.
RS/6000 Scientific and Technical Computing: POWER3 Introduction and Tuning Guide - Copia archiviata (PDF), su redbooks.ibm.com. URL consultato il 27 luglio 2006 (archiviato dall'url originale il 21 luglio 2006). (Ch. 2.1 pp. 7-8)
Functional Principles of Cache Memory - Multiporting., su alasir.com. URL consultato il 28 febbraio 2017 (archiviato dall'url originale il 4 dicembre 2016).
BM RS/6000 Scientific and Technical Computing: POWER3 Introduction and Tuning Guide (Ch 7.1 p. 89) - Copia archiviata (PDF), su redbooks.ibm.com. URL consultato il 27 luglio 2006 (archiviato dall'url originale il 21 luglio 2006).
BM RS/6000 Scientific and Technical Computing: POWER3 Introduction and Tuning Guide Ch. 2.1 p. 7 - ch 7.1 p.89 - Copia archiviata (PDF), su redbooks.ibm.com. URL consultato il 27 luglio 2006 (archiviato dall'url originale il 21 luglio 2006).
"POWER4 System Microarchitecture", http://www.cc.gatech.edu/~bader/COURSES/UNM/ece637-Fall2003/papers/TDF02.pdf Archiviato il 7 novembre 2013 in Internet Archive.
BM PowerPC 476FP L2 Cache Core Databook - Copia archiviata (PDF), su www-01.ibm.com. URL consultato il 1º novembre 2016 (archiviato dall'url originale il 18 dicembre 2014).
Cache Organization and Memory Management of the Intel Nehalem Computer Architecture - Trent Rolf - Copia archiviata (PDF), su rolfed.com. URL consultato il 26 settembre 2014 (archiviato dall'url originale il 30 agosto 2014).
MPC750UM/D 12/2001 Rev. 1 MPC750 RISC Microprocessor Family User's Manual - http://www.freescale.com/files/32bit/doc/ref_manual/MPC750UM.pdf Archiviato il 24 settembre 2015 in Internet Archive.
AMD64 Technology - AMD64 Architecture Programmer's Manual Volume 2: System Programming - http://developer.amd.com/wordpress/media/2012/10/24593_APM_v21.pdf Archiviato il 3 marzo 2016 in Internet Archive.
Mark S. Papamarcos and Janak H. Patel. In ISCA '84: Proceedings of the 11th annual international symposium on Computer architecture, pages 348{354, New York, NY, USA, 1984. ACM - https://web.archive.org/web/20150521112759/http://www.researchgate.net/profile/Janak_Patel4/publication/220771512_A_Low-Overhead_Coherence_Solution_for_Multiprocessors_with_Private_Cache_Memories/links/00463519b8d139e451000000.pdf
IBM POWER Systems Overview - https://computing.llnl.gov/tutorials/ibm_sp/ Archiviato il 27 maggio 2010 in Internet Archive.
NUMA Architecture - http://www.dba-oracle.com/real_application_clusters_rac_grid/numa.html Archiviato il 9 ottobre 2016 in Internet Archive.
Directory-based CacheCoherence – Parallel Computer Architecture par. 1.3.2 pg. 48 – http://www.dte.eis.uva.es/Docencia/ETSII/SMP/archivos/archibak/culler.pdf Archiviato il 18 maggio 2015 in Internet Archive.
Directory-based CacheCoherence - Parallel Computer Architecture ch. 8 pg. 513 - http://www.dte.eis.uva.es/Docencia/ETSII/SMP/archivos/archibak/culler.pdf Archiviato il 18 maggio 2015 in Internet Archive.

wisc.edu

research.cs.wisc.edu

Cache Coherence Techniques for Multicore Processors - Michael R. Marty - http://research.cs.wisc.edu/multifacet/theses/michael_marty_phd.pdf

wustl.edu

cse.wustl.edu

AMD Opteron Shared Memory MP Systems - http://www.cse.wustl.edu/~roger/569M.s09/28_AMD_Hammer_MP_HC_v8.pdf
Proceedings of the 17th Annual International Symposium on Computer Architecture, IEEE 1990, pages 148-159; D. Lenosky et al: The Directory-Based Cache Coherency Protocol for DASH Multiprocessor - http://www.cse.wustl.edu/~roger/569M.s09/p148-lenoski.pdf