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Mark LaPedus (2016年1月20日). “5nm Fab Challenges”. 2016年1月27日時点のオリジナルよりアーカイブ。2018年12月26日閲覧。 “Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it.
Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS).”
Mark LaPedus (2016年1月20日). “5nm Fab Challenges”. 2016年1月27日時点のオリジナルよりアーカイブ。2018年12月26日閲覧。 “Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it.
Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS).”
