FinFET (Japanese Wikipedia)

Analysis of information sources in references of the Wikipedia article "FinFET" in Japanese language version.

Last modified: 21:56:47, 12 March 2026 (UTC)

Ref.Un. Ref.Website

Global rank Japanese rank

33doi.org

2^nd place

3^rd place

11berkeley.edu

621^st place

1,656^th place

11web.archive.org

1^st place

11dlia.ir

low place

11psu.edu

299^th place

1,653^rd place

11nvidia.com

2,958^th place

2,190^th place

11intel.com

1,727^th place

1,575^th place

11techradar.com

1,513^th place

3,716^th place

berkeley.edu (Global: 621^st place; Japanese: 1,656^th place)

people.eecs.berkeley.edu

Xuejue Huang; Wen-Chin Lee; Kuo, C. et al. (May 2001). “Sub-50 nm P-channel FinFET”. IEEE Transactions on Electron Devices 48 (5): 880–886. doi:10.1109/16.918235.

dlia.ir (Global: low place; Japanese: low place)

Hisamoto, D.; Kaga, T.; Takeda, E. (June 1991). “Impact of the vertical SOI 'DELTA' structure on planar device technology”. IEEE Transactions on Electron Devices 38 (6): 1419–1424. doi:10.1109/16.81634. オリジナルの2016-12-01時点におけるアーカイブ。.

doi.org (Global: 2^nd place; Japanese: 3^rd place)

Xuejue Huang; Wen-Chin Lee; Kuo, C. et al. (May 2001). “Sub-50 nm P-channel FinFET”. IEEE Transactions on Electron Devices 48 (5): 880–886. doi:10.1109/16.918235.
Hisamoto, D.; Kaga, T.; Takeda, E. (June 1991). “Impact of the vertical SOI 'DELTA' structure on planar device technology”. IEEE Transactions on Electron Devices 38 (6): 1419–1424. doi:10.1109/16.81634. オリジナルの2016-12-01時点におけるアーカイブ。.
Chenming Hu; Bokor, J. et al. (December 2000). “FinFET-a self-aligned double-gate MOSFET scalable to 20 nm”. IEEE Transactions on Electron Devices 47 (12): 2320–2325. doi:10.1109/16.887014.

intel.com (Global: 1,727^th place; Japanese: 1,575^th place)

download.intel.com

Bohr, Mark (2011年5月). “Intel's Revolutionary 22 nm Transistor Technology”. intel.com. 2018年4月18日閲覧。

nvidia.com (Global: 2,958^th place; Japanese: 2,190^th place)

NVidia Pascal Microarchitecture

psu.edu (Global: 299^th place; Japanese: 1,653^rd place)

citeseerx.ist.psu.edu

Chenming Hu; Bokor, J. et al. (December 2000). “FinFET-a self-aligned double-gate MOSFET scalable to 20 nm”. IEEE Transactions on Electron Devices 47 (12): 2320–2325. doi:10.1109/16.887014.

techradar.com (Global: 1,513^th place; Japanese: 3,716^th place)

Grabham, Dan (May 6, 2011). “Intel's Tri-Gate transistors: everything you need to know”. TechRadar (英語). 2018年4月19日閲覧.

web.archive.org (Global: 1^st place; Japanese: 1^st place)

Hisamoto, D.; Kaga, T.; Takeda, E. (June 1991). “Impact of the vertical SOI 'DELTA' structure on planar device technology”. IEEE Transactions on Electron Devices 38 (6): 1419–1424. doi:10.1109/16.81634. オリジナルの2016-12-01時点におけるアーカイブ。.

FinFET (Japanese Wikipedia)

berkeley.edu (Global: 621st place; Japanese: 1,656th place)

people.eecs.berkeley.edu

dlia.ir (Global: low place; Japanese: low place)

doi.org (Global: 2nd place; Japanese: 3rd place)

intel.com (Global: 1,727th place; Japanese: 1,575th place)

download.intel.com

nvidia.com (Global: 2,958th place; Japanese: 2,190th place)

psu.edu (Global: 299th place; Japanese: 1,653rd place)