FinFET (Japanese Wikipedia)

Analysis of information sources in references of the Wikipedia article "FinFET" in Japanese language version.

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berkeley.edu

people.eecs.berkeley.edu

Xuejue Huang; Wen-Chin Lee; Kuo, C. et al. (May 2001). “Sub-50 nm P-channel FinFET”. IEEE Transactions on Electron Devices 48 (5): 880–886. doi:10.1109/16.918235.

dlia.ir

Hisamoto, D.; Kaga, T.; Takeda, E. (June 1991). “Impact of the vertical SOI 'DELTA' structure on planar device technology”. IEEE Transactions on Electron Devices 38 (6): 1419–1424. doi:10.1109/16.81634. オリジナルの2016-12-01時点におけるアーカイブ。.

doi.org

Xuejue Huang; Wen-Chin Lee; Kuo, C. et al. (May 2001). “Sub-50 nm P-channel FinFET”. IEEE Transactions on Electron Devices 48 (5): 880–886. doi:10.1109/16.918235.
Hisamoto, D.; Kaga, T.; Takeda, E. (June 1991). “Impact of the vertical SOI 'DELTA' structure on planar device technology”. IEEE Transactions on Electron Devices 38 (6): 1419–1424. doi:10.1109/16.81634. オリジナルの2016-12-01時点におけるアーカイブ。.
Chenming Hu; Bokor, J. et al. (December 2000). “FinFET-a self-aligned double-gate MOSFET scalable to 20 nm”. IEEE Transactions on Electron Devices 47 (12): 2320–2325. doi:10.1109/16.887014.

intel.com

download.intel.com

Bohr, Mark (May 2011). “Intel's Revolutionary 22 nm Transistor Technology”. intel.com. April 18, 2018閲覧。

nvidia.com

NVidia Pascal Microarchitecture

psu.edu

citeseerx.ist.psu.edu

Chenming Hu; Bokor, J. et al. (December 2000). “FinFET-a self-aligned double-gate MOSFET scalable to 20 nm”. IEEE Transactions on Electron Devices 47 (12): 2320–2325. doi:10.1109/16.887014.

techradar.com

Grabham, Dan (May 6, 2011). “Intel's Tri-Gate transistors: everything you need to know” (英語). TechRadar April 19, 2018閲覧。

web.archive.org

Hisamoto, D.; Kaga, T.; Takeda, E. (June 1991). “Impact of the vertical SOI 'DELTA' structure on planar device technology”. IEEE Transactions on Electron Devices 38 (6): 1419–1424. doi:10.1109/16.81634. オリジナルの2016-12-01時点におけるアーカイブ。.