Sohn, J. B. (janeiro de 2017). «A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution». IEEE Journal of Solid-State Circuits. 52 (1): 250–260. Bibcode:2017IJSSC..52..250S. doi:10.1109/JSSC.2016.2602221
Shilov, Anton (1 de agosto de 2016). «SKHynix Adds HBM2 to Catalog». Anandtech. Consultado em 1 de agosto de 2016. Arquivado do original em 2 de agosto de 2016
Sohn, J. B. (janeiro de 2017). «A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution». IEEE Journal of Solid-State Circuits. 52 (1): 250–260. Bibcode:2017IJSSC..52..250S. doi:10.1109/JSSC.2016.2602221
Where Are DRAM Interfaces Headed?Arquivado em 2018-06-15 no Wayback Machine // EETimes, 18/4/2014 "The Hybrid Memory Cube (HMC) and a competing technology called High-Bandwidth Memory (HBM) are aimed at computing and networking applications. These approaches stack multiple DRAM chips atop a logic chip."
Where Are DRAM Interfaces Headed?Arquivado em 2018-06-15 no Wayback Machine // EETimes, 18/4/2014 "The Hybrid Memory Cube (HMC) and a competing technology called High-Bandwidth Memory (HBM) are aimed at computing and networking applications. These approaches stack multiple DRAM chips atop a logic chip."
Shilov, Anton (1 de agosto de 2016). «SKHynix Adds HBM2 to Catalog». Anandtech. Consultado em 1 de agosto de 2016. Arquivado do original em 2 de agosto de 2016