N.P.Jouppi. «Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers.» — 17th Annual International Symposium on Computer Architecture, 1990. Proceedings., DOI:10.1109/ISCA.1990.134547
IBM POWER4 Processor Review. IxbtlabsАрхивная копия от 13 июля 2011 на Wayback Machine «An important feature of the L3 cache is a capability to combine separate caches of POWER4 chips up to 4 (128 MBytes) which allows using address interleaving to speed up the access.»
IBM POWER4 Processor Review. IxbtlabsАрхивная копия от 13 июля 2011 на Wayback Machine «An important feature of the L3 cache is a capability to combine separate caches of POWER4 chips up to 4 (128 MBytes) which allows using address interleaving to speed up the access.»
