RISC-V (Serbian Wikipedia)

Analysis of information sources in references of the Wikipedia article "RISC-V" in Serbian language version.

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2tomshardware.com

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1drive.google.com

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acm.org (Global: 1,185^th place; Serbian: 1,193^rd place)

dl.acm.org

Patterson, David A.; Ditzel, David R. (1980-10-01). „The case for the reduced instruction set computer”. SIGARCH Comput. Archit. News. 8 (6): 25—33. ISSN 0163-5964. doi:10.1145/641914.641917.

berkeley.edu (Global: 580^th place; Serbian: 551^st place)

www2.eecs.berkeley.edu

Asanović, Krste; Patterson, David A. (6. 8. 2014). Instruction Sets Should Be Free: The Case For RISC-V (PDF). EECS Department, University of California, Berkeley. UCB/EECS-2014-146.
Asanović, Krste. „Instruction Sets Should be Free” (PDF). U.C. Berkeley Technical Reports. Regents of the University of California. Приступљено 15. 11. 2016.
„Tech Reports | EECS at UC Berkeley”. www2.eecs.berkeley.edu. Приступљено 2025-05-16.
„SOAR Architecture | EECS at UC Berkeley”. www2.eecs.berkeley.edu. Приступљено 2025-05-16.
Asanović, Krste. „The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA” (PDF). U.C. Berkeley Technical Reports. Regents of the University of California. Приступљено 13. 5. 2011.

debian.org (Global: 3,857^th place; Serbian: 6,140^th place)

wiki.debian.org

„RISC-V - Debian Wiki”. wiki.debian.org. Приступљено 2024-08-13.
„RISC-V - Debian Wiki”. wiki.debian.org. Приступљено 2024-08-13.

lists.debian.org

„riscv64 is now an official architecture”. lists.debian.org. Приступљено 2024-08-13.

doi.org (Global: 2^nd place; Serbian: 4^th place)

Nguyen, Phuc-Vinh; Tran, Thi-Thu-Trang; Diep, Phuoc-Loc; Le, Duc-Hung (септембар 2018). „A Low-Power ASIC Implementation of Multi-Core OpenSPARC T1 Processor on 90nm CMOS Process”. 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE. стр. 95—100. ISBN 978-1-5386-6689-0. doi:10.1109/MCSoC2018.2018.00027.
Patterson, David A.; Ditzel, David R. (1980-10-01). „The case for the reduced instruction set computer”. SIGARCH Comput. Archit. News. 8 (6): 25—33. ISSN 0163-5964. doi:10.1145/641914.641917.

drive.google.com (Global: 1,343^rd place; Serbian: 1,078^th place)

„B Standard Extension for Bit Manipulation Instructions”. RISC-V International. април 2024.

eetimes.eu (Global: low place; Serbian: low place)

„RISC-V To Move HQ to Switzerland Amid Trade War Concerns”. EE Times Europe. 28. 11. 2019.

extremetech.com (Global: 4,667^th place; Serbian: low place)

Hruska, Joel (21. 8. 2014). „RISC rides again: New RISC-V architecture hopes to battle ARM and x86 by being totally open source”. ExtremeTech.

fedoramagazine.org (Global: low place; Serbian: low place)

Hanlon, Neil (2025-02-19). „RISC-V and Fedora: All Aboard!”. Fedora Magazine (на језику: енглески). Приступљено 2025-02-21.

fedoraproject.org (Global: low place; Serbian: low place)

„Architectures - Fedora Project Wiki”. fedoraproject.org. Приступљено 2025-02-21.

gentoo.org (Global: low place; Serbian: low place)

wiki.gentoo.org

„Project:RISC-V - Gentoo wiki”. wiki.gentoo.org. Приступљено 2025-02-11.

github.com (Global: 383^rd place; Serbian: 1,569^th place)

„The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191213” (PDF).
„The RISC-V Instruction Set Manual Volume II: Privileged Architecture Document Version 20211203” (PDF).
„Vector Extension”. RISC-V International. новембар 2021.

ieee.org (Global: 652^nd place; Serbian: 1,147^th place)

ieeexplore.ieee.org

Nguyen, Phuc-Vinh; Tran, Thi-Thu-Trang; Diep, Phuoc-Loc; Le, Duc-Hung (септембар 2018). „A Low-Power ASIC Implementation of Multi-Core OpenSPARC T1 Processor on 90nm CMOS Process”. 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE. стр. 95—100. ISBN 978-1-5386-6689-0. doi:10.1109/MCSoC2018.2018.00027.

kernel.org (Global: 4,558^th place; Serbian: low place)

docs.kernel.org

„CPU Architectures — The Linux Kernel documentation”. docs.kernel.org. Приступљено 2024-08-20.

opensuse.org (Global: low place; Serbian: low place)

en.opensuse.org

„openSUSE Project Wiki”. opensuse.org. Приступљено 2025-02-25.

riscv.org (Global: low place; Serbian: low place)

„About RISC-V”. RISC-V International.
„Frequently Asked Questions (FAQ) – RISC-V International” (на језику: енглески). Приступљено 2024-08-20.
„Linux 5.17 Adds Support For "The First Usable, Low-Cost RISC-V Platform" | Michael Larabel, Phoronix – RISC-V International” (на језику: енглески). 2022. Приступљено 2024-08-20.
„Contributors - RISC-V Foundation”. RISC-V Foundation (на језику: енглески). Архивирано из оригинала 07. 09. 2018. г. Приступљено 2025-05-16.
„About RISC-V International”. RISC-V International (на језику: енглески). Приступљено 2025-05-26.

theregister.com (Global: 3,700^th place; Serbian: low place)

Connatser, Matthew (2024-08-13). „Akeana debuts RISC-V CPU designs on $100M budget, longs for an Arm wrestle”. The Register. Приступљено 2024-08-19.
Connatser, Matthew. „World's first RISC-V laptop with Ubuntu preloaded touts AI smarts and octa-core chip”. The Register. Приступљено 2024-08-19.

tomshardware.com (Global: 2,976^th place; Serbian: 8,424^th place)

Anton Shilov (2024-03-20). „Alibaba claims it will launch a server-grade RISC-V processor this year”. Tom's Hardware (на језику: енглески). Приступљено 2024-08-19.
Aleksandar Kostovic (2021-07-12). „Libre-SOC Releases First Non-IBM OpenPOWER Chip in Decade”. Tom's Hardware (на језику: енглески). Приступљено 2024-08-20.

web.archive.org (Global: 1^st place; Serbian: 1^st place)

„Contributors - RISC-V Foundation”. RISC-V Foundation (на језику: енглески). Архивирано из оригинала 07. 09. 2018. г. Приступљено 2025-05-16.

worldcat.org (Global: 5^th place; Serbian: 12^th place)

Patterson, David A.; Ditzel, David R. (1980-10-01). „The case for the reduced instruction set computer”. SIGARCH Comput. Archit. News. 8 (6): 25—33. ISSN 0163-5964. doi:10.1145/641914.641917.