Кеш централне процесорске јединице (Serbian Wikipedia)

Analysis of information sources in references of the Wikipedia article "Кеш централне процесорске јединице" in Serbian language version.

refsWebsite

Global rank Serbian rank

8web.archive.org

1^st place

4doi.org

2^nd place

4^th place

3semanticscholar.org

11^th place

23^rd place

3bitsavers.org

4,153^rd place

3,983^rd place

3acm.org

1,185^th place

1,193^rd place

2psu.edu

207^th place

370^th place

2intel.com

1,118^th place

2,622^nd place

2anandtech.com

1,383^rd place

4,986^th place

2ieee.org

652^nd place

1,147^th place

1neu.edu

low place

9,010^th place

1washington.edu

1,067^th place

757^th place

1stanford.edu

179^th place

200^th place

1irisa.fr

low place

1wisc.edu

1,045^th place

937^th place

1chilton-computing.org.uk

low place

1linuxjournal.com

8,246^th place

low place

1archive.org

6^th place

5^th place

1cmu.edu

1,564^th place

2,673^rd place

1uci.edu

3,063^rd place

6,546^th place

1archive.today

14^th place

22^nd place

1sandpile.org

low place

1webcitation.org

24^th place

56^th place

1princeton.edu

741^st place

729^th place

1hp.com

3,975^th place

6,753^rd place

acm.org (Global: 1,185^th place; Serbian: 1,193^rd place)

dl.acm.org

André Seznec (1993). „A Case for Two-Way Skewed-Associative Caches”. ACM Sigarch Computer Architecture News. 21 (2): 169—178. doi:10.1145/173682.165152. Приступљено 13. 12. 2007.

acm.org

„The Processor-Memory performance gap”. acm.org. Архивирано из оригинала 27. 4. 2012. г. Приступљено 8. 11. 2007.

portal.acm.org

"Chip Design Thwarts Sneak Attack on Data" by Sally Adee 2009 discusses "A novel cache architecture with enhanced performance and security" [1] [2] Архивирано на веб-сајту Wayback Machine (6. март 2012) by Zhenghong Wang and Ruby B. Lee: (abstract) "Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice."

anandtech.com (Global: 1,383^rd place; Serbian: 4,986^th place)

„Intel Iris Pro 5200 Graphics Review: Core i7-4950HQ Tested”. AnandTech. Архивирано из оригинала 29. 03. 2016. г. Приступљено 16. 9. 2013.
Anand Lal Shimpi (5. 10. 2012). „Intel's Haswell Architecture Analyzed”. AnandTech. Архивирано из оригинала 28. 06. 2013. г. Приступљено 20. 10. 2013.

archive.org (Global: 6^th place; Serbian: 5^th place)

Jouppi, N.P. (1990). „Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers”. [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture. стр. 364–373. ISBN 0-8186-2047-1. S2CID 6157765. doi:10.1109/ISCA.1990.134547.

archive.today (Global: 14^th place; Serbian: 22^nd place)

Anand Lal Shimpi (5. 10. 2012). „Intel's Haswell Architecture Analyzed”. AnandTech. Архивирано из оригинала 28. 06. 2013. г. Приступљено 20. 10. 2013.

bitsavers.org (Global: 4,153^rd place; Serbian: 3,983^rd place)

GE (јануар 1968). GE-645 System Manual (PDF). Архивирано из оригинала (PDF) 14. 03. 2012. г. Приступљено 04. 11. 2013.
IBM (фебруар 1972). IBM System/360 Model 67 Functional Characteristics (PDF). Third Edition. GA27-2719-2. Архивирано из оригинала (PDF) 14. 03. 2012. г. Приступљено 04. 11. 2013.
IBM (јун 1968). IBM System/360 Model 85 Functional Characteristics (PDF). SECOND EDITION. A22-6916-1. Архивирано из оригинала (PDF) 07. 09. 2011. г. Приступљено 04. 11. 2013.

chilton-computing.org.uk (Global: low place; Serbian: low place)

Kilburn, T.; Payne, R. B.; Howarth, D. J. (1961). „The Atlas Supervisor”. Computers - Key to Total Systems Control. Conferences Proceedings. 20 Proceedings of the Eastern Joint Computer Conference Washington, D.C. Macmillan. стр. 279—294.

cmu.edu (Global: 1,564^th place; Serbian: 2,673^rd place)

cs.cmu.edu

Gu, Leon; Dipti Motiani (2003). „Trace Cache” (PDF). Приступљено 6. 10. 2013.

doi.org (Global: 2^nd place; Serbian: 4^th place)

André Seznec (1993). „A Case for Two-Way Skewed-Associative Caches”. ACM Sigarch Computer Architecture News. 21 (2): 169—178. doi:10.1145/173682.165152. Приступљено 13. 12. 2007.
Jouppi, N.P. (1990). „Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers”. [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture. стр. 364–373. ISBN 0-8186-2047-1. S2CID 6157765. doi:10.1109/ISCA.1990.134547.
Rotenberg, E.; Bennett, S.; Smith, J.E. (1996). Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching. стр. 24—34. ISBN 0-8186-7641-8. S2CID 221908866. doi:10.1109/MICRO.1996.566447.
Solomon, Baruch; Mendelson, Avi; Orenstein, Doron; Almog, Yoav; Ronny Ronen (2001). „Micro-Operation Cache: A Power Aware Frontend for Variable Instruction Length ISA” (PDF). ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581). Intel. стр. 4—9. ISBN 1-58113-371-5. S2CID 10934861. doi:10.1109/LPE.2001.945363. Приступљено 6. 10. 2013.

hp.com (Global: 3,975^th place; Serbian: 6,753^rd place)

hpl.hp.com

„CACTI”. Hpl.hp.com. Архивирано из оригинала 21. 11. 2009. г. Приступљено 2. 5. 2010.

ieee.org (Global: 652^nd place; Serbian: 1,147^th place)

ieeexplore.ieee.org

IEEE Xplore - Phased set associative cache design for reduced power consumption. Ieeexplore.ieee.org (2009-08-11). Приступљено 2013-07-30.

spectrum.ieee.org

"Chip Design Thwarts Sneak Attack on Data" by Sally Adee 2009 discusses "A novel cache architecture with enhanced performance and security" [1] [2] Архивирано на веб-сајту Wayback Machine (6. март 2012) by Zhenghong Wang and Ruby B. Lee: (abstract) "Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice."

intel.com (Global: 1,118^th place; Serbian: 2,622^nd place)

ark.intel.com

„Products (Formerly Crystal Well)”. Intel. Приступљено 15. 9. 2013.
„Intel® Xeon® Processor E7 Family”. Intel. Приступљено 10. 10. 2013.

irisa.fr (Global: low place; Serbian: low place)

* Micro-Architecture "Skewed-associative caches have … major advantages over conventional set-associative caches."

linuxjournal.com (Global: 8,246^th place; Serbian: low place)

„Understanding Caching”. Linux Journal. Приступљено 2. 5. 2010.

neu.edu (Global: low place; Serbian: 9,010^th place)

ccs.neu.edu

Gene Cooperman. "Cache Basics", 2003

princeton.edu (Global: 741^st place; Serbian: 729^th place)

palms.princeton.edu

"Chip Design Thwarts Sneak Attack on Data" by Sally Adee 2009 discusses "A novel cache architecture with enhanced performance and security" [1] [2] Архивирано на веб-сајту Wayback Machine (6. март 2012) by Zhenghong Wang and Ruby B. Lee: (abstract) "Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice."

psu.edu (Global: 207^th place; Serbian: 370^th place)

citeseer.ist.psu.edu

André Seznec. „A Case for Two-Way Skewed-Associative Caches”. Приступљено 13. 12. 2007.
Rotenberg, E.; Bennett, S.; Smith, J.E. (1996). Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching. стр. 24—34. ISBN 0-8186-7641-8. S2CID 221908866. doi:10.1109/MICRO.1996.566447.

sandpile.org (Global: low place; Serbian: low place)

„AMD K8”. Sandpile.org. Архивирано из оригинала 15. 5. 2007. г. Приступљено 2. 6. 2007.

semanticscholar.org (Global: 11^th place; Serbian: 23^rd place)

api.semanticscholar.org

Jouppi, N.P. (1990). „Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers”. [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture. стр. 364–373. ISBN 0-8186-2047-1. S2CID 6157765. doi:10.1109/ISCA.1990.134547.
Rotenberg, E.; Bennett, S.; Smith, J.E. (1996). Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching. стр. 24—34. ISBN 0-8186-7641-8. S2CID 221908866. doi:10.1109/MICRO.1996.566447.
Solomon, Baruch; Mendelson, Avi; Orenstein, Doron; Almog, Yoav; Ronny Ronen (2001). „Micro-Operation Cache: A Power Aware Frontend for Variable Instruction Length ISA” (PDF). ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581). Intel. стр. 4—9. ISBN 1-58113-371-5. S2CID 10934861. doi:10.1109/LPE.2001.945363. Приступљено 6. 10. 2013.

stanford.edu (Global: 179^th place; Serbian: 200^th place)

* "Advanced Caching Techniques" Архивирано на веб-сајту Wayback Machine (7. септембар 2012) by C. Kozyrakis

uci.edu (Global: 3,063^rd place; Serbian: 6,546^th place)

cecs.uci.edu

Solomon, Baruch; Mendelson, Avi; Orenstein, Doron; Almog, Yoav; Ronny Ronen (2001). „Micro-Operation Cache: A Power Aware Frontend for Variable Instruction Length ISA” (PDF). ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581). Intel. стр. 4—9. ISBN 1-58113-371-5. S2CID 10934861. doi:10.1109/LPE.2001.945363. Приступљено 6. 10. 2013.

washington.edu (Global: 1,067^th place; Serbian: 757^th place)

cs.washington.edu

Ben Dugan. "Concerning Caches". 2002

web.archive.org (Global: 1^st place; Serbian: 1^st place)

* "Advanced Caching Techniques" Архивирано на веб-сајту Wayback Machine (7. септембар 2012) by C. Kozyrakis
„Intel Iris Pro 5200 Graphics Review: Core i7-4950HQ Tested”. AnandTech. Архивирано из оригинала 29. 03. 2016. г. Приступљено 16. 9. 2013.
„AMD K8”. Sandpile.org. Архивирано из оригинала 15. 5. 2007. г. Приступљено 2. 6. 2007.
GE (јануар 1968). GE-645 System Manual (PDF). Архивирано из оригинала (PDF) 14. 03. 2012. г. Приступљено 04. 11. 2013.
IBM (фебруар 1972). IBM System/360 Model 67 Functional Characteristics (PDF). Third Edition. GA27-2719-2. Архивирано из оригинала (PDF) 14. 03. 2012. г. Приступљено 04. 11. 2013.
IBM (јун 1968). IBM System/360 Model 85 Functional Characteristics (PDF). SECOND EDITION. A22-6916-1. Архивирано из оригинала (PDF) 07. 09. 2011. г. Приступљено 04. 11. 2013.
"Chip Design Thwarts Sneak Attack on Data" by Sally Adee 2009 discusses "A novel cache architecture with enhanced performance and security" [1] [2] Архивирано на веб-сајту Wayback Machine (6. март 2012) by Zhenghong Wang and Ruby B. Lee: (abstract) "Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice."
„CACTI”. Hpl.hp.com. Архивирано из оригинала 21. 11. 2009. г. Приступљено 2. 5. 2010.

webcitation.org (Global: 24^th place; Serbian: 56^th place)

„The Processor-Memory performance gap”. acm.org. Архивирано из оригинала 27. 4. 2012. г. Приступљено 8. 11. 2007.

wisc.edu (Global: 1,045^th place; Serbian: 937^th place)

cs.wisc.edu

„Cache performance of SPEC CPU2000”. Cs.wisc.edu. Приступљено 2. 5. 2010.

Кеш централне процесорске јединице (Serbian Wikipedia)

acm.org (Global: 1,185th place; Serbian: 1,193rd place)

dl.acm.org

acm.org

portal.acm.org

anandtech.com (Global: 1,383rd place; Serbian: 4,986th place)

archive.org (Global: 6th place; Serbian: 5th place)

archive.today (Global: 14th place; Serbian: 22nd place)

bitsavers.org (Global: 4,153rd place; Serbian: 3,983rd place)

chilton-computing.org.uk (Global: low place; Serbian: low place)

cmu.edu (Global: 1,564th place; Serbian: 2,673rd place)

cs.cmu.edu

doi.org (Global: 2nd place; Serbian: 4th place)

hp.com (Global: 3,975th place; Serbian: 6,753rd place)

hpl.hp.com

ieee.org (Global: 652nd place; Serbian: 1,147th place)

ieeexplore.ieee.org

spectrum.ieee.org

intel.com (Global: 1,118th place; Serbian: 2,622nd place)

ark.intel.com

irisa.fr (Global: low place; Serbian: low place)

linuxjournal.com (Global: 8,246th place; Serbian: low place)

neu.edu (Global: low place; Serbian: 9,010th place)

ccs.neu.edu

princeton.edu (Global: 741st place; Serbian: 729th place)

palms.princeton.edu

psu.edu (Global: 207th place; Serbian: 370th place)

citeseer.ist.psu.edu

sandpile.org (Global: low place; Serbian: low place)

semanticscholar.org (Global: 11th place; Serbian: 23rd place)

api.semanticscholar.org

stanford.edu (Global: 179th place; Serbian: 200th place)

uci.edu (Global: 3,063rd place; Serbian: 6,546th place)

cecs.uci.edu

washington.edu (Global: 1,067th place; Serbian: 757th place)

cs.washington.edu

web.archive.org (Global: 1st place; Serbian: 1st place)

webcitation.org (Global: 24th place; Serbian: 56th place)

wisc.edu (Global: 1,045th place; Serbian: 937th place)

cs.wisc.edu

acm.org (Global: 1,185^th place; Serbian: 1,193^rd place)

anandtech.com (Global: 1,383^rd place; Serbian: 4,986^th place)

archive.org (Global: 6^th place; Serbian: 5^th place)

archive.today (Global: 14^th place; Serbian: 22^nd place)

bitsavers.org (Global: 4,153^rd place; Serbian: 3,983^rd place)

cmu.edu (Global: 1,564^th place; Serbian: 2,673^rd place)

doi.org (Global: 2^nd place; Serbian: 4^th place)

hp.com (Global: 3,975^th place; Serbian: 6,753^rd place)

ieee.org (Global: 652^nd place; Serbian: 1,147^th place)

intel.com (Global: 1,118^th place; Serbian: 2,622^nd place)

linuxjournal.com (Global: 8,246^th place; Serbian: low place)

neu.edu (Global: low place; Serbian: 9,010^th place)

princeton.edu (Global: 741^st place; Serbian: 729^th place)

psu.edu (Global: 207^th place; Serbian: 370^th place)

semanticscholar.org (Global: 11^th place; Serbian: 23^rd place)

stanford.edu (Global: 179^th place; Serbian: 200^th place)

uci.edu (Global: 3,063^rd place; Serbian: 6,546^th place)

washington.edu (Global: 1,067^th place; Serbian: 757^th place)

web.archive.org (Global: 1^st place; Serbian: 1^st place)

webcitation.org (Global: 24^th place; Serbian: 56^th place)

wisc.edu (Global: 1,045^th place; Serbian: 937^th place)