三維晶片 (Chinese Wikipedia)

Analysis of information sources in references of the Wikipedia article "三維晶片" in Chinese language version.

refsWebsite

Global rank Chinese rank

26web.archive.org

1^st place

6gradient-da.com

low place

3eetimes.com

3,722^nd place

2,427^th place

2devhardware.com

low place

2future-fab.com

low place

1tomshardware.com

2,976^th place

2,557^th place

1sciencedaily.com

993^rd place

1,142^nd place

1gatech.edu

4,448^th place

3,595^th place

1ieee.org

652^nd place

712^th place

1realworldtech.com

low place

1psu.edu

207^th place

628^th place

1electronicdesign.com

low place

6,822^nd place

1ucdavis.edu

1,873^rd place

2,601^st place

1tezzaron.com

low place

1eetasia.com

low place

1semi.org

low place

1i-micronews.com

low place

1electroiq.com

low place

1monolithic3d.com

low place

devhardware.com

Developer, Shed. "3D Processors, Stacking Core". September 20, 2005. http://www.devhardware.com/c/a/Computer-Processors/3D-Processor-Technology/ （页面存档备份，存于互联网档案馆）,
Developer, Shed. "3D Processors, Stacking Core". September 20, 2005. http://www.devhardware.com/c/a/Computer-Processors/3D-Processor-Technology/1/ （页面存档备份，存于互联网档案馆）

eetasia.com

http://www.eetasia.com/ART_8800485666_480300_NT_fcb98510.HTM （页面存档备份，存于互联网档案馆） "EDA's big three unready for 3D chip packaging". EE Times Asia, October 25, 2007]

eetimes.com

Johnson, R Colin. "3-D chip stacks standardized". July 10, 2008. http://www.eetimes.com/electronics-news/4077835/3-D-chip-stacks-standardized （页面存档备份，存于互联网档案馆）
"3-D chip stacks standardized". EE Times November 7, 2008. [2012-10-29]. （原始内容存档于2012-09-30）.
存档副本. [2012-10-29]. （原始内容存档于2012-10-05）.

electroiq.com

存档副本. [2011-01-27]. （原始内容存档于2011-03-14）. "Si, glass interposers for 3D packaging: analysts' takes". Advanced Packaging August 10, 2010]

electronicdesign.com

"3D IC Technology Delivers The Total Package" 存档副本. [2011-01-27]. （原始内容存档于2010-10-31）. Electronic Design July 02, 2010

future-fab.com

James J-Q Lu, Ken Rose, & Susan Vitkavage "3D Integration: Why, What, Who, When?" 存档副本. [2008-01-22]. （原始内容存档于2008-02-12）. Future Fab Intl. Volume 23, 2007
Robert Patti, "Impact of Wafer-Level 3D Stacking on the Yield of ICs". Future Fab Intl. Volume 23, 2007. [2012-10-29]. （原始内容存档于2014-05-17）.

gatech.edu

arch.ece.gatech.edu

3D-MAPS project webpage at Georgia Tech 存档副本. [2012-04-02]. （原始内容存档于2015-03-08）.

gradient-da.com

存档副本. [2012-10-29]. （原始内容存档于2014-08-14）.
存档副本. [2012-10-29]. （原始内容存档于2014-08-14）.
存档副本 (PDF). [2021-02-10]. （原始内容存档 (PDF)于2012-05-23）.
存档副本 (PDF). [2012-10-29]. （原始内容存档 (PDF)于2012-05-23）.
存档副本 (PDF). [2012-10-29]. （原始内容存档 (PDF)于2013-09-23）.
存档副本 (PDF). [2012-10-29]. （原始内容存档 (PDF)于2012-05-23）.

i-micronews.com

"ADVANCED PACKAGING: 3D TSV Technologies Scenarios: Via First or Via Last? 2010 report". Yole report, 2010. [2012-10-29]. （原始内容存档于2014-05-17）.

ieee.org

ieeexplore.ieee.org

D.Y. Chen, W. Chiou, M.F. Chen, T. Wang, K. Ching, H. Tu, W.J. Wu, C. Yu, K. Yang, H.B. Chang, M. Tseng, C.W. Hsiao, Y.J. Lu, H.P. Hu, Y.C. Lin, C. Hsu, W. Shue, C. Yu. Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking. [2021-08-09]. （原始内容存档于2021-11-22）.

monolithic3d.com

存档副本. [2012-10-29]. （原始内容存档于2020-09-28）.

psu.edu

cse.psu.edu

Xiangyu Dong and Yuan Xie, "System-level Cost Analysis and Design Exploration for 3D ICs", Proc. of Asia and South Pacific Design Automation Conference, 2009, 存档副本. [2010-05-20]. （原始内容存档于2010-04-24）.

realworldtech.com

Real World Technologies. "3D Integration: A Revolution in Design". May 2, 2007. http://realworldtech.com/page.cfm?ArticleID=RWT050207213241&p=6 （页面存档备份，存于互联网档案馆）

sciencedaily.com

Science Daily. "3-D Computer Processor: 'Rochester Cube' Points Way To More Powerful Chip Designs". September 17, 2008. [2012-10-29]. （原始内容存档于2021-03-08）.

semi.org

"SEMI International Standards Program Forms 3D Stacked IC Standards Committee". SEMI press release December 7, 2010. [2012-10-29]. （原始内容存档于2014-05-17）.

tezzaron.com

"3D-ICs and Integrated Circuit Security" http://www.tezzaron.com/about/papers/3D-ICs_and_Integrated_Circuit_Security.pdf （页面存档备份，存于互联网档案馆） Tezzaron Semiconductor, 2008

tomshardware.com

Seguin, Steve. "World's First Stacked 3D Processor Created". September 16, 2008

ucdavis.edu

ece.ucdavis.edu

William J. Dally, "Future Directions for On-Chip Interconnection Networks" page 17, http://www.ece.ucdavis.edu/~ocin06/talks/dally.pdf （页面存档备份，存于互联网档案馆） Computer Systems Laboratory Stanford University, 2006

web.archive.org

Science Daily. "3-D Computer Processor: 'Rochester Cube' Points Way To More Powerful Chip Designs". September 17, 2008. [2012-10-29]. （原始内容存档于2021-03-08）.
3D-MAPS project webpage at Georgia Tech 存档副本. [2012-04-02]. （原始内容存档于2015-03-08）.
D.Y. Chen, W. Chiou, M.F. Chen, T. Wang, K. Ching, H. Tu, W.J. Wu, C. Yu, K. Yang, H.B. Chang, M. Tseng, C.W. Hsiao, Y.J. Lu, H.P. Hu, Y.C. Lin, C. Hsu, W. Shue, C. Yu. Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking. [2021-08-09]. （原始内容存档于2021-11-22）.
Real World Technologies. "3D Integration: A Revolution in Design". May 2, 2007. http://realworldtech.com/page.cfm?ArticleID=RWT050207213241&p=6 （页面存档备份，存于互联网档案馆）
Developer, Shed. "3D Processors, Stacking Core". September 20, 2005. http://www.devhardware.com/c/a/Computer-Processors/3D-Processor-Technology/ （页面存档备份，存于互联网档案馆）,
Developer, Shed. "3D Processors, Stacking Core". September 20, 2005. http://www.devhardware.com/c/a/Computer-Processors/3D-Processor-Technology/1/ （页面存档备份，存于互联网档案馆）
Xiangyu Dong and Yuan Xie, "System-level Cost Analysis and Design Exploration for 3D ICs", Proc. of Asia and South Pacific Design Automation Conference, 2009, 存档副本. [2010-05-20]. （原始内容存档于2010-04-24）.
"3D IC Technology Delivers The Total Package" 存档副本. [2011-01-27]. （原始内容存档于2010-10-31）. Electronic Design July 02, 2010
James J-Q Lu, Ken Rose, & Susan Vitkavage "3D Integration: Why, What, Who, When?" 存档副本. [2008-01-22]. （原始内容存档于2008-02-12）. Future Fab Intl. Volume 23, 2007
William J. Dally, "Future Directions for On-Chip Interconnection Networks" page 17, http://www.ece.ucdavis.edu/~ocin06/talks/dally.pdf （页面存档备份，存于互联网档案馆） Computer Systems Laboratory Stanford University, 2006
Johnson, R Colin. "3-D chip stacks standardized". July 10, 2008. http://www.eetimes.com/electronics-news/4077835/3-D-chip-stacks-standardized （页面存档备份，存于互联网档案馆）
"3D-ICs and Integrated Circuit Security" http://www.tezzaron.com/about/papers/3D-ICs_and_Integrated_Circuit_Security.pdf （页面存档备份，存于互联网档案馆） Tezzaron Semiconductor, 2008
Robert Patti, "Impact of Wafer-Level 3D Stacking on the Yield of ICs". Future Fab Intl. Volume 23, 2007. [2012-10-29]. （原始内容存档于2014-05-17）.
http://www.eetasia.com/ART_8800485666_480300_NT_fcb98510.HTM （页面存档备份，存于互联网档案馆） "EDA's big three unready for 3D chip packaging". EE Times Asia, October 25, 2007]
"3-D chip stacks standardized". EE Times November 7, 2008. [2012-10-29]. （原始内容存档于2012-09-30）.
"SEMI International Standards Program Forms 3D Stacked IC Standards Committee". SEMI press release December 7, 2010. [2012-10-29]. （原始内容存档于2014-05-17）.
"ADVANCED PACKAGING: 3D TSV Technologies Scenarios: Via First or Via Last? 2010 report". Yole report, 2010. [2012-10-29]. （原始内容存档于2014-05-17）.
存档副本. [2011-01-27]. （原始内容存档于2011-03-14）. "Si, glass interposers for 3D packaging: analysts' takes". Advanced Packaging August 10, 2010]
存档副本. [2012-10-29]. （原始内容存档于2012-10-05）.
存档副本. [2012-10-29]. （原始内容存档于2020-09-28）.
存档副本. [2012-10-29]. （原始内容存档于2014-08-14）.
存档副本. [2012-10-29]. （原始内容存档于2014-08-14）.
存档副本 (PDF). [2021-02-10]. （原始内容存档 (PDF)于2012-05-23）.
存档副本 (PDF). [2012-10-29]. （原始内容存档 (PDF)于2012-05-23）.
存档副本 (PDF). [2012-10-29]. （原始内容存档 (PDF)于2013-09-23）.
存档副本 (PDF). [2012-10-29]. （原始内容存档 (PDF)于2012-05-23）.