逻辑综合 (Chinese Wikipedia)

Analysis of information sources in references of the Wikipedia article "逻辑综合" in Chinese language version.

refsWebsite

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4web.archive.org

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1computerhistory.org

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archive.org

Stephen Brown, Zvonko Vranesic. Fundamentals of Digital Logic with Verilog Design. McGraw-Hill Education. 2002. ISBN 0-07-283878-7.
Naveed A. Sherwani. Algorithms for VLSI physical design automation 3rd. Kluwer Academic Publishers. 1999: 4. ISBN 978-0-7923-8393-2.
Donald E. Thomas, Philip R. Moorby. 硬件描述语言Verilog（第四版）（英文名：The Verilog Hardware Description Language (Fouth Edition)）. 清华大学出版社. 2001: 168. ISBN 7-900635-36-X.

berkeley.edu

eecs.berkeley.edu

SIS: A System for Sequential Circuit Synthesis. EECS, College of Engineering, UC Berkeley. [2012-07-09]. （原始内容存档于2021-02-25）.

computerhistory.org

1966 - Computer Aided Design Tools Developed for ICs. Computer History Museum. [2012-07-09]. （原始内容存档于2015-12-22）.

eetimes.com

archives.eetimes.com

EETimes: High-level synthesis rollouts enable ESL^{[失效連結]}

nyu.edu

Claude Shannon. New York University. [2012-07-09]. （原始内容存档于2020-04-08）.

ucla.edu

cadlab.cs.ucla.edu

RASP: FPGA/CPLD Technology Mapping and Synthesis Package. UCLA. [2012-07-09]. （原始内容存档于2021-02-25）.

web.archive.org

Claude Shannon. New York University. [2012-07-09]. （原始内容存档于2020-04-08）.
SIS: A System for Sequential Circuit Synthesis. EECS, College of Engineering, UC Berkeley. [2012-07-09]. （原始内容存档于2021-02-25）.
RASP: FPGA/CPLD Technology Mapping and Synthesis Package. UCLA. [2012-07-09]. （原始内容存档于2021-02-25）.
1966 - Computer Aided Design Tools Developed for ICs. Computer History Museum. [2012-07-09]. （原始内容存档于2015-12-22）.